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ORCIDKenichi Ichino
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2000 – 2009
- 2008
[j3]Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa:
Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development. J. Inf. Process. Syst. 4(4): 121-132 (2008)- 2004
- [j2]Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits. IEICE Trans. Inf. Syst. 87-D(3): 586-591 (2004) - [c4]Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki:
Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters. Asian Test Symposium 2004: 190-195 - 2003
- [j1]Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Seed Selection Procedure for LFSR-Based Random Pattern Generators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3063-3071 (2003) - [c3]Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
A seed selection procedure for LFSR-based random pattern generators. ASP-DAC 2003: 869-874 - [c2]Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka:
Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. Asian Test Symposium 2003: 28-31 - 2001
- [c1]Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara:
Hybrid BIST Using Partially Rotational Scan. Asian Test Symposium 2001: 379-384
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