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Journal Articles
- 2024
[j22]Cristian Tirelli
, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, Jose Angel Miranda, David Atienza, Laura Pozzi:
SAT-Based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs. ACM J. Emerg. Technol. Comput. Syst. 20(3): 8:1-8:26 (2024)- [j21]Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Mohit Gupta, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor:
An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1018-1031 (2024) - 2023
- [j20]Silvio Zanoli, Giovanni Ansaloni, Tomás Teijeiro, David Atienza:
Event-based sampled ECG morphology reconstruction through self-similarity. Comput. Methods Programs Biomed. 240: 107712 (2023) - [j19]Joshua Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza:
ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning. IEEE Trans. Computers 72(7): 1985-1998 (2023) - [j18]Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Miroslav Vasic, David Atienza:
Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 2-15 (2023) - [j17]Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza:
Overflow-free Compute Memories for Edge AI Acceleration. ACM Trans. Embed. Comput. Syst. 22(5s): 121:1-121:23 (2023) - [j16]Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza:
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. IEEE Trans. Emerg. Top. Comput. 11(2): 358-372 (2023) - 2022
- [j15]Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón Quirós, David Atienza:
A Hardware/Software Co-Design Vision for Deep Learning at the Edge. IEEE Micro 42(6): 48-54 (2022) - [j14]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi:
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 840-853 (2022) - 2021
- [j13]Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi:
DB4HLS: A Database of High-Level Synthesis Design Space Explorations. IEEE Embed. Syst. Lett. 13(4): 194-197 (2021) - [j12]Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi:
Cluster-Based Heuristic for High Level Synthesis Design Space Exploration. IEEE Trans. Emerg. Top. Comput. 9(1): 35-43 (2021) - 2020
- [j11]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi, Sherief Reda:
Approximate Logic Synthesis: A Survey. Proc. IEEE 108(12): 2195-2213 (2020) - [j10]Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi:
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3736-3747 (2020) - 2019
- [j9]Loris Duch, Soumya Basu, Miguel Peón Quirós, Giovanni Ansaloni, Laura Pozzi, David Atienza:
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing. IEEE Embed. Syst. Lett. 11(2): 50-53 (2019) - [j8]Georgios Zacharopoulos, Lorenzo Ferretti, Emanuele Giaquinta, Giovanni Ansaloni, Laura Pozzi:
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 741-754 (2019) - 2017
- [j7]Rubén Braojos, Daniele Bortolotti, Andrea Bartolini, Giovanni Ansaloni, Luca Benini, David Atienza:
A Synchronization-Based Hybrid-Memory Multi-Core Architecture for Energy-Efficient Biomedical Signal Processing. IEEE Trans. Computers 66(4): 575-585 (2017) - [j6]Loris Duch, Soumya Basu, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza:
HEAL-WEAR: An Ultra-Low Power Heterogeneous System for Bio-Signal Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2448-2461 (2017) - [j5]Soumya Basu, Loris Duch, Rubén Braojos, Giovanni Ansaloni, Laura Pozzi, David Atienza:
An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery. ACM Trans. Embed. Comput. Syst. 16(5s): 159:1-159:19 (2017) - 2016
- [j4]Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, Laura Pozzi, David Atienza:
Inexact-aware architecture design for ultra-low power bio-signal analysis. IET Comput. Digit. Tech. 10(6): 306-314 (2016) - 2014
- [j3]Rubén Braojos, Ivan Beretta, Giovanni Ansaloni, David Atienza:
Early Classification of Pathological Heartbeats on Wireless Body Sensor Nodes. Sensors 14(12): 22532-22551 (2014) - 2012
- [j2]Giovanni Ansaloni, Kazuyuki Tanimura, Laura Pozzi, Nikil D. Dutt:
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1803-1816 (2012) - 2011
- [j1]Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
EGRA: A Coarse Grained Reconfigurable Architectural Template. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1062-1074 (2011)
Conference and Workshop Papers
- 2024
- [c45]Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui, Reveil Lucas, Cristell Maneux:
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. DATE 2024: 1-6 - [c44]Alireza Amirshahi, Giovanni Ansaloni, David Atienza:
Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures. PARMA-DITAM 2024: 2:1-2:13 - [c43]Anna Burdina, Gabriel Catel Torres, Pasquale Davide Schiavone, Miguel Peón Quirós, Giovanni Ansaloni, David Atienza, Marina Zapater:
Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware. ISLPED 2024: 1-6 - [c42]Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor:
DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD. ISVLSI 2024: 204-209 - 2023
- [c41]Rafael Medina, Joshua Kein, Giovanni Ansaloni, Marina Zapater, Sergi Abadal, Eduard Alarcón, David Atienza:
System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms. ASP-DAC 2023: 561-566 - [c40]Alireza Amirshahi, Joshua Alexander Harrison Klein, Giovanni Ansaloni, David Atienza:
TiC-SAT: Tightly-Coupled Systolic Accelerator for Transformers. ASP-DAC 2023: 657-663 - [c39]Rubén Rodríguez Álvarez, Benoît W. Denkinger, Juan Sapriza, Jose Angel Miranda Calero, Giovanni Ansaloni, David Atienza Alonso:
An Open-Hardware Coarse-Grained Reconfigurable Array for Edge Computing. CF 2023: 391-392 - [c38]Michael T. Niemier, Xiaobo Sharon Hu, Liu Liu, Mohammad Mehdi Sharifi, Ian O'Connor, David Atienza, Giovanni Ansaloni, Can Li, Asif Khan, Daniel C. Ralph:
Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures. DATE 2023: 1-10 - [c37]Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza:
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. VLSI-SoC 2023: 1-6 - [c36]Rafael Medina, Darong Huang, Giovanni Ansaloni, Marina Zapater, David Atienza:
REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal. VLSI-SoC 2023: 1-6 - 2022
- [c35]Flavio Ponzina, Miguel Peón Quirós, Giovanni Ansaloni, David Atienza:
An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs. COINS 2022: 1-6 - [c34]Lorenzo Ferretti, Giovanni Ansaloni, Renaud Marquis, Tomás Teijeiro, Philippe Ryvlin, David Atienza, Laura Pozzi:
INCLASS: Incremental Classification Strategy for Self-Aware Epileptic Seizure Detection. DATE 2022: 1449-1454 - [c33]Halima Najibi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza:
Thermal and Power-Aware Run-time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays. ACM Great Lakes Symposium on VLSI 2022: 223-228 - [c32]Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. ACM Great Lakes Symposium on VLSI 2022: 249-254 - [c31]Rafael Medina, Joshua Kein, Yasir Mahmood Qureshi, Marina Zapater, Giovanni Ansaloni, David Atienza:
Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures. LASCAS 2022: 1-4 - 2021
- [c30]Joshua Klein, Alexandre Levisse, Giovanni Ansaloni, David Atienza, Marina Zapater, Martino Dazzi, Geethan Karunaratne, Irem Boybat, Abu Sebastian, Davide Rossi, Francesco Conti, Elana Pereira de Santana, Peter Haring Bolívar, Mohamed Saeed, Renato Negra, Zhenxing Wang, Kun-Ta Wang, Max Christian Lemme, Akshay Jain, Robert Guirado, Hamidreza Taghvaee, Sergi Abadal:
Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH). CF 2021: 191-193 - [c29]William Andrew Simon, Valérian Ray, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza:
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding. DAC 2021: 805-810 - [c28]Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. DATE 2021: 1881-1886 - [c27]Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. ISVLSI 2021: 164-169 - 2020
- [c26]Giovanni Ansaloni, Ilaria Scarabottolo, Laura Pozzi:
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design. ARC 2020: 14-29 - 2019
- [c25]Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi:
Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. DAC 2019: 40 - [c24]Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi, Amir Aminifar, David Atienza, Leila Cammoun, Philippe Ryvlin:
Tailoring SVM Inference for Resource-Efficient ECG-Based Epilepsy Monitors. DATE 2019: 948-951 - [c23]Georgios Zacharopoulos, Lorenzo Ferretti, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi:
Compiler-Assisted Selection of Hardware Acceleration Candidates from Application Source Code. ICCD 2019: 129-137 - 2018
- [c22]Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi:
A partitioning strategy for exploring error-resilience in circuits: work-in-progress. CASES 2018: 5:1-5:2 - [c21]Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi:
Circuit carving: A methodology for the design of approximate hardware. DATE 2018: 545-550 - [c20]Lorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi:
Lattice-Traversing Design Space Exploration for High Level Synthesis. ICCD 2018: 210-217 - [c19]Georgios Zacharopoulos, Andrea Barbon, Giovanni Ansaloni, Laura Pozzi:
Machine Learning Approach for Loop Unrolling Factor Prediction in High Level Synthesis. HPCS 2018: 91-97 - [c18]Soumya Basu, Loris Duch, Miguel Peón Quirós, David Atienza, Giovanni Ansaloni, Laura Pozzi:
Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications. ISCAS 2018: 1-5 - 2016
- [c17]Loris Duch, Soumya Basu, Rubén Braojos, David Atienza, Giovanni Ansaloni, Laura Pozzi:
A multi-core reconfigurable architecture for ultra-low power bio-signal analysis. BioCAS 2016: 416-419 - [c16]Daniele Bortolotti, Andrea Bartolini, Luca Benini, V. Rajesh Pamula, Nick Van Helleputte, Chris Van Hoof, Marian Verhelst, Tobias Gemmeke, Rubén Braojos Lopez, Giovanni Ansaloni, David Atienza, Pierre Vandergheynst:
PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms. Conf. Computing Frontiers 2016: 309-314 - [c15]Rubén Braojos, David Atienza, Mohamed M. Sabry Aly, Tony F. Wu, H.-S. Philip Wong, Subhasish Mitra, Giovanni Ansaloni:
Nano-engineered architectures for ultra-low power wireless body sensor nodes. CODES+ISSS 2016: 23:1-23:10 - 2015
- [c14]Soumya Basu, Pablo García Del Valle, Georgios Karakonstantis, Giovanni Ansaloni, David Atienza:
Heterogeneous Error-Resilient Scheme for Spectral Analysis in Ultra-Low Power Wearable Electrocardiogram Devices. ISVLSI 2015: 268-273 - 2014
- [c13]Frédéric Giroud, Pascal Persechini, Pierre-François Ruedi, Giovanni Ansaloni, Rubén Braojos, F. Viemon, Frederic Masson:
Live demonstration: ECG sensor interface in a low power SoC for wireless portable ECG monitoring. BioCAS 2014: 187 - [c12]Jelena Milosevic, Andreas Dittrich, Alberto Ferrante, Miroslaw Malek, Camilo Rojas Quiros, Rubén Braojos, Giovanni Ansaloni, David Atienza:
Risk Assessment of Atrial Fibrillation: a Failure Prediction Approach. CinC 2014: 801-804 - [c11]Rubén Braojos, Hossein Mamaghanian, Alair Dias Junior, Giovanni Ansaloni, David Atienza, Francisco J. Rincón, Srinivasan Murali:
Ultra-Low Power Design of Wearable Cardiac Monitoring Systems. DAC 2014: 17:1-17:6 - [c10]Rubén Braojos, Ahmed Yasir Dogan, Ivan Beretta, Giovanni Ansaloni, David Atienza:
Hardware/software approach for code synchronization in low-power multi-core sensor nodes. DATE 2014: 1-6 - [c9]Hossein Mamaghanian, Giovanni Ansaloni, David Atienza, Pierre Vandergheynst:
Power-efficient joint compressed sensing of multi-lead ECG signals. ICASSP 2014: 4409-4412 - 2013
- [c8]Ahmed Yasir Dogan, Rubén Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg, David Atienza:
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms. DATE 2013: 396-399 - [c7]Rubén Braojos, Giovanni Ansaloni, David Atienza:
A methodology for embedded classification of heartbeats using random projections. DATE 2013: 899-904 - 2012
- [c6]Rubén Braojos, Giovanni Ansaloni, David Atienza, Francisco J. Rincón:
Embedded real-time ECG delineation methods: A comparative evaluation. BIBE 2012: 99-104 - [c5]Marios Milis, Kyriacos Michaelides, Anastasis Kounoudes, Giovanni Ansaloni, David Atienza, Frédéric Giroud, Pierre-François Ruedi, Frederic Masson:
IcyHeart: Highly integrated ultra-low-power SoC solution for unobtrusive and energy efficient wireless cardiac monitoring: Research project for the benefit of specific groups (FP7, Capacities). BIBE 2012: 105-109 - 2011
- [c4]Giovanni Ansaloni, Laura Pozzi, Kazuyuki Tanimura, Nikil D. Dutt:
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. DATE 2011: 1513-1516 - 2009
- [c3]Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. DATE 2009: 542-547 - 2008
- [c2]Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi:
Compiling custom instructions onto expression-grained reconfigurable architectures. CASES 2008: 51-60 - [c1]Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
Design and Architectural Exploration of Expression-Grained Reconfigurable Arrays. SASP 2008: 26-33
Informal and Other Publications
- 2024
- [i8]Corey Lammie, Flavio Ponzina, Yuxuan Wang, Joshua Klein, Marina Zapater, Irem Boybat, Abu Sebastian, Giovanni Ansaloni, David Atienza:
LionHeart: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles. CoRR abs/2401.09420 (2024) - [i7]Cristian Tirelli, Juan Sapriza, Rubén Rodríguez Álvarez, Lorenzo Ferretti, Benoît W. Denkinger, Giovanni Ansaloni, Jose Angel Miranda Calero, David Atienza, Laura Pozzi:
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs. CoRR abs/2402.12834 (2024) - [i6]Alireza Amirshahi, Maedeh H. Toosi, Siamak Mohammadi, Stefano Albini, Pasquale Davide Schiavone, Giovanni Ansaloni, Amir Aminifar, David Atienza:
MetaWearS: A Shortcut in Wearable Systems Lifecycle with Only a Few Shots. CoRR abs/2408.01988 (2024) - 2023
- [i5]Alireza Amirshahi, Giovanni Ansaloni, David Atienza:
Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures. CoRR abs/2312.13000 (2023) - 2022
- [i4]Joshua Klein, Irem Boybat, Yasir Mahmood Qureshi, Martino Dazzi, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, Abu Sebastian, David Atienza:
ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning. CoRR abs/2205.10042 (2022) - [i3]Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza:
Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. CoRR abs/2209.06108 (2022) - [i2]Pengbo Yu, Alexandre Levisse, Mohit Gupta, Timon Evenblij, Giovanni Ansaloni, Francky Catthoor, David Atienza:
A Soft SIMD Based Energy Efficient Computing Microarchitecture. CoRR abs/2212.09358 (2022) - 2021
- [i1]Lorenzo Ferretti, Jihye Kwon, Giovanni Ansaloni, Giuseppe Di Guglielmo, Luca P. Carloni, Laura Pozzi:
DB4HLS: A Database of High-Level Synthesis Design Space Explorations. CoRR abs/2101.00587 (2021)
Coauthor Index
David Atienza
aka: David Atienza Alonso
aka: David Atienza Alonso
[j22] [j21] [j20] [j19] [j18] [j17] [j16] [j15] [j9] [j7] [j6] [j5] [j4] [j3] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c24] [c18] [c17] [c16] [c15] [c14] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [i8] [i7] [i6] [i5] [i4] [i3] [i2]
Rubén Braojos
aka: Rubén Braojos Lopez
aka: Rubén Braojos Lopez
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