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ORCIDMaged Ghoneima
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2020 – today
- 2020
[c45]Hossam O. Ahmed
, Maged Ghoneima, Mohamed Dessouky:
Reconfigurable Systolic-based Pyramidal Neuron Block for CNN Acceleration on FPGA. ICSET 2020: 179-184
2010 – 2019
- 2019
- [j12]Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky:
Systolic-based pyramidal neuron accelerator blocks for convolutional neural network. Microelectron. J. 89: 16-22 (2019) - 2018
- [j11]Noha Shaarawy, Ahmed A. M. Emara, Ahmed M. El-Naggar, Mohammed E. Elbtity, Maged Ghoneima, Ahmed G. Radwan:
Design and analysis of 2T2M hybrid CMOS-Memristor based RRAM. Microelectron. J. 73: 75-85 (2018) - [c44]Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky:
Pyramidal Neuron Architectures for AcceleratingDeep Neural Networks on FPGA. AHS 2018: 104-111 - [c43]I. Mohamed Elzayat, M. Ahmed Saad, M. Mohamed Mostafa, R. Mahmoud Hassan, Hossam Abd El Munim, Maged Ghoneima, M. Saeed Darweesh, Hassan Mostafa:
Real-Time Car Detection-Based Depth Estimation Using Mono Camera. ICM 2018: 248-251 - [c42]Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky:
High-Speed 2D Parallel MAC Unit Hardware Accelerator for Convolutional Neural Network. IntelliSys (1) 2018: 655-663 - [c41]Ahmed Mahmoud, Loay Ehab, Mohamed Reda, Mostafa Abdelaleem, Hossam Abd El Munim, Maged Ghoneima, M. Saeed Darweesh, Hassan Mostafa:
Real-Time Lane Detection-Based Line Segment Detection. NGCAS 2018: 57-61 - 2017
- [j10]Taher Kourany, Maged Ghoneima, Emad Hegazi, Yehea Ismail:
PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine. Integr. 58: 9-21 (2017) - [c40]Youmna Magdy, Omar M. Shehata, Mohamed Abdelaziz, Maged Ghoneima, Farid A. Tolbah:
Metaheuristic optimization in path planning of autonomous vehicles under the ATOM framework. ICVES 2017: 32-37 - 2016
- [c39]Eslam Khafagy, Ahmed Hatab, Amr Rashed, Ahmed A. M. Emara, Maged Ghoneima:
A fixed function 3D rendering hardware for mobile applications. ICM 2016: 113-116 - [c38]Islam S. M. Khalil, Ahmet Fatih Tabak, Abdelrahman Hosney, Abdallah Mohamed, Anke Klingner, Maged Ghoneima, Metin Sitti:
Sperm-shaped magnetic microrobots: Fabrication using electrospinning, modeling, and characterization. ICRA 2016: 1939-1944 - [c37]Amr Lotfy, Maged Ghoneima, Mohamed Abdel-Moneum:
A fast locking hybrid TDC-BB ADPLL utilizing proportional derivative digital loop filter and power gated DCO. ISCAS 2016: 1646-1649 - [c36]Ahmed Emad, Mohamed A. E. Mahmoud, Maged Ghoneima, Mohamed Dessouky:
Modeling and analysis of stretching strain in clamped-clamped beams for energy harvesting. MWSCAS 2016: 1-4 - [c35]Mustafa Khairallah, Maged Ghoneima:
Tile-based modular architecture for accelerating homomorphic function evaluation on FPGA. MWSCAS 2016: 1-4 - [c34]Taher Kourany, Maged Ghoneima, Emad Hegazi, Yehea Ismail:
PASSIOT: A pareto-optimal multi-objective optimization approach for synthesis of analog circuits using sobol' indices-based engine. MWSCAS 2016: 1-4 - [c33]Mostafa Shadoufa, Mohamed Mahmoud, Maged Ghoneima, Mohamed Dessouky:
Optimization of the output power of a frequency-up conversion piezoelectric energy harvester. MWSCAS 2016: 1-4 - [i1]Mustafa Khairallah, Maged Ghoneima:
Tile-Based Modular Architecture for Accelerating Homomorphic Function Evaluation on FPGA. IACR Cryptol. ePrint Arch. 2016: 725 (2016) - 2015
- [c32]Ramy N. Tadros, Ahmed H. Abdelrahman, Maged Ghoneima, Yehea Ismail:
A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme. ICEAC 2015: 1-4 - [c31]Mostafa Shadoufa, Ahmed Emad, Maged Ghoneima, Mohamed A. E. Mahmoud, Mohamed Dessouky:
Structure optimization for efficient AlN piezoelectric energy harvesters. ICECS 2015: 527-530 - [c30]Noha Shaarawy, Maged Ghoneima, Ahmed G. Radwan:
2T2M memristor-based memory cell for higher stability RRAM modules. ISCAS 2015: 1418-1421 - [c29]Mustafa Khairallah, Maged Ghoneima:
New polynomial basis versatile multiplier over GF(2m) for low-power on-chip crypto-systems. ISCAS 2015: 1438-1441 - [c28]Ahmed A. M. Emara, Maged Ghoneima:
A reference-less multilevel memristor based RRAM module. MWSCAS 2015: 1-4 - 2014
- [c27]Ramy N. Tadros, Abdelrahman H. Elsayed, Maged Ghoneima, Yehea I. Ismail:
A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks. ISCAS 2014: 1520-1523 - [c26]Abdelrahman H. Elsayed, Ramy N. Tadros, Maged Ghoneima, Yehea I. Ismail:
Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks. ISCAS 2014: 2752-2755 - 2012
- [c25]Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor:
Modeling the response of Bang-Bang digital PLLs to phase error perturbations. CICC 2012: 1-4 - [c24]Sally Safwat, Amr Lotfy, Maged Ghoneima, Yehea I. Ismail:
A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. ISCAS 2012: 1371-1374 - [c23]Ezz El-Din O. Hussein, Sally Safwat, Maged Ghoneima, Yehea I. Ismail:
A 16Gbps low power self-timed SerDes transceiver for multi-core communication. ISCAS 2012: 1660-1663 - [c22]Ahmed El Kholy, Maged Ghoneima, Khaled Sharaf:
A 0.8V 6.4µW compact mixed-signal front-end for neural implants. ISCAS 2012: 2223-2226 - [c21]Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdelsalam, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor:
A novel digital loop filter architecture for bang-bang ADPLL. SoCC 2012: 45-50 - 2011
- [j9]Maged Ghoneima, Yong Lian, Gabriele Manganaro, Shahriar Mirabbasi, Christian Piguet, Wouter A. Serdijn:
Guest Editorial Special Issue on ISCAS 2010. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(7): 1457 (2011) - [c20]Amr M. Lotfy, Maged Ghoneima, Mohamed Abdel-Moneum:
A novel power gated digitally controlled oscillator. ICEAC 2011: 1-4 - [c19]Sally Safwat, Maged Ghoneima, Yehea I. Ismail:
A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients. ICEAC 2011: 1-4 - [c18]Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail:
A 12Gbps all digital low power SerDes transceiver for on-chip networking. ISCAS 2011: 1419-1422 - [c17]Mina Raymond, Maged Ghoneima, Yehea I. Ismail:
A dynamic calibration scheme for on-chip process and temperature variations. ISCAS 2011: 2047-2050
2000 – 2009
- 2009
- [j8]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De:
SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 384-394 (2009) - [j7]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2020-2032 (2009) - 2008
- [j6]Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De:
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1904-1910 (2008) - 2007
- [j5]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De:
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. VLSI Design 2007: 95402:1-95402:12 (2007) - 2006
- [j4]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 821-836 (2006) - [j3]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(9): 1928-1933 (2006) - [c16]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De:
Reducing the data switching activity of serialized datastreams. ISCAS 2006 - [c15]Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De:
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED 2006: 79-84 - [c14]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De:
Reducing the Data Switching Activity on Serial Link Buses. ISQED 2006: 425-432 - 2005
- [j2]Maged Ghoneima, Yehea I. Ismail:
Optimum positioning of interleaved repeaters in bidirectional buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 461-469 (2005) - [c13]Ja Chun Ku, Maged Ghoneima, Yehea I. Ismail:
The importance of including thermal effects in estimating the effectiveness of power reduction techniques. CICC 2005: 301-304 - [c12]Maged Ghoneima, Ehsan Atoofian, Amirali Baniasadi, Yehea I. Ismail:
Low-power prediction based data transfer architecture. CICC 2005: 313-316 - [c11]Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail:
Physical limitations on the bit-rate of on-chip interconnects. ACM Great Lakes Symposium on VLSI 2005: 13-19 - [c10]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Serial-link bus: a low-power on-chip bus architecture. ICCAD 2005: 541-546 - [c9]Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail:
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD 2005: 253-257 - [c8]Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De:
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) 2005: 592-595 - [c7]Maged Ghoneima, Yehea I. Ismail:
Accurate decoupling of capacitively coupled buses. ISCAS (4) 2005: 4146-4149 - 2004
- [j1]Maged Ghoneima, Yehea I. Ismail:
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1348-1359 (2004) - [c6]Maged Ghoneima, Yehea I. Ismail:
Formal derivation of optimal active shielding for low-power on-chip buses. ICCAD 2004: 800-807 - [c5]Maged Ghoneima, Yehea I. Ismail:
Low power coupling-based encoding for on-chip buses. ISCAS (2) 2004: 325-328 - [c4]Maged Ghoneima, Yehea I. Ismail:
Effect of relative delay on the dissipated energy in coupled interconnects. ISCAS (2) 2004: 525-528 - [c3]Maged Ghoneima, Yehea I. Ismail:
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. ISLPED 2004: 66-69 - [c2]Maged Ghoneima, Yehea I. Ismail:
Low-power on-chip bus architecture using dynamic relative delays. SoCC 2004: 233-236 - 2003
- [c1]Maged Ghoneima, Yehea I. Ismail:
Optimum positioning of interleaved repeaters In bidirectional buses. DAC 2003: 586-591
Coauthor Index
aka: Yehea Ismail
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