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ORCIDNaveen Suda
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2020 – today
- 2024
[i12]Junxiao Shen
, Matthias De Lange, Xuhai Orson Xu, Enmin Zhou, Ran Tan, Naveen Suda, Maciej Lazarewicz, Per Ola Kristensson, Amy Karlson, Evan Strasnick:
Towards Open-World Gesture Recognition. CoRR abs/2401.11144 (2024)- 2022
- [c10]Kartikeya Bhardwaj, Milos Milosavljevic, Liam O'Neil, Dibakar Gope, Ramon Matas Navarro, Alex Chalfin, Naveen Suda, Lingchuan Meng, Danny Loh:
Collapsible Linear Blocks for Super-Efficient Super Resolution. MLSys 2022 - 2021
- [j4]Kartikeya Bhardwaj, Naveen Suda, Radu Marculescu:
EdgeAl: A Vision for Deep Learning in the IoT Era. IEEE Des. Test 38(4): 37-43 (2021) - [i11]Kartikeya Bhardwaj, Milos Milosavljevic, Alex Chalfin, Naveen Suda, Liam O'Neil, Dibakar Gope, Lingchuan Meng, Ramon Matas Navarro, Danny Loh:
Collapsible Linear Blocks for Super-Efficient Super Resolution. CoRR abs/2103.09404 (2021)
2010 – 2019
- 2019
- [c9]Jeya Vikranth Jeyakumar, Liangzhen Lai, Naveen Suda, Mani B. Srivastava:
SenseHAR: a robust virtual activity sensor for smartphones and wearables. SenSys 2019: 15-28 - [i10]Kartikeya Bhardwaj, Naveen Suda, Radu Marculescu:
Dream Distillation: A Data-Independent Model Compression Framework. CoRR abs/1905.07072 (2019) - [i9]Kartikeya Bhardwaj, Naveen Suda, Radu Marculescu:
EdgeAI: A Vision for Deep Learning in IoT Era. CoRR abs/1910.10356 (2019) - 2018
- [j3]Yufei Ma, Naveen Suda, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler. Integr. 62: 14-23 (2018) - [c8]Liangzhen Lai, Naveen Suda:
Enabling deep learning at the IoT edge. ICCAD 2018: 135 - [c7]Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Vikas Chandra, Hadi Esmaeilzadeh:
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network. ISCA 2018: 764-775 - [i8]Liangzhen Lai, Naveen Suda, Vikas Chandra:
Not All Ops Are Created Equal! CoRR abs/1801.04326 (2018) - [i7]Liangzhen Lai, Naveen Suda, Vikas Chandra:
CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs. CoRR abs/1801.06601 (2018) - [i6]Yue Zhao, Meng Li, Liangzhen Lai, Naveen Suda, Damon Civin, Vikas Chandra:
Federated Learning with Non-IID Data. CoRR abs/1806.00582 (2018) - [i5]Liangzhen Lai, Naveen Suda:
Rethinking Machine Learning Development and Deployment for Edge Devices. CoRR abs/1806.07846 (2018) - 2017
- [c6]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo:
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ASP-DAC 2017: 21-22 - [c5]Minkyu Kim, Abinash Mohanty, Deepak Kadetotad, Naveen Suda, Luning Wei, Pooja Saseendran, Xiaofei He, Yu Cao, Jae-sun Seo:
A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS. ISCAS 2017: 1-4 - [i4]Liangzhen Lai, Naveen Suda, Vikas Chandra:
Deep Convolutional Neural Network Inference with Floating-point Weights and Fixed-point Activations. CoRR abs/1703.03073 (2017) - [i3]Meng Li, Liangzhen Lai, Naveen Suda, Vikas Chandra, David Z. Pan:
PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control. CoRR abs/1709.06161 (2017) - [i2]Yundong Zhang, Naveen Suda, Liangzhen Lai, Vikas Chandra:
Hello Edge: Keyword Spotting on Microcontrollers. CoRR abs/1711.07128 (2017) - [i1]Hardik Sharma, Jongse Park, Naveen Suda, Liangzhen Lai, Benson Chau, Joon Kyung Kim, Vikas Chandra, Hadi Esmaeilzadeh:
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks. CoRR abs/1712.01507 (2017) - 2016
- [j2]Naveen Suda, Jounghyuk Suh, Nagib Hakim, Yu Cao, Bertan Bakkaloglu:
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 181-190 (2016) - [c4]Naveen Suda, Vikas Chandra, Ganesh Dasika, Abinash Mohanty, Yufei Ma, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks. FPGA 2016: 16-25 - [c3]Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. FPL 2016: 1-8 - [c2]Abinash Mohanty, Naveen Suda, Minkyu Kim, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao:
High-performance face detection with CPU-FPGA acceleration. ISCAS 2016: 117-120 - 2015
- [c1]Raveesh Magod, Naveen Suda, Vadim Ivanov, Ravi Balasingam, Bertan Bakkaloglu:
A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference. CICC 2015: 1-4 - 2013
- [j1]Jounghyuk Suh, Naveen Suda, Cheng Xu, Nagib Hakim, Yu Cao, Bertan Bakkaloglu:
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1369-1380 (2013)
Coauthor Index
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