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ORCIDLi Jiang 0002
- > Home > Persons > Li Jiang 0002
Publications
- 2024
[c82]Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Naifeng Jing, Li Jiang, Xiaoyao Liang:
Watt: A Write-Optimized RRAM-Based Accelerator for Attention. Euro-Par (2) 2024: 107-120- [c80]Yilong Zhao, Mingyu Gao, Fangxin Liu, Yiwei Hu, Zongwu Wang, Han Lin, Jin Li, He Xian, Hanlin Dong, Tao Yang, Naifeng Jing, Xiaoyao Liang, Li Jiang:
UM-PIM: DRAM-based PIM with Uniform & Shared Memory Space. ISCA 2024: 644-659 - 2023
- [j20]Zhuoran Song
, Heng Lu, Li Jiang, Naifeng Jing, Xiaoyao Liang:
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2238-2251 (2023) - [c76]Zhuoran Song, Heng Lu, Gang Li, Li Jiang, Naifeng Jing, Xiaoyao Liang:
PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation. DATE 2023: 1-6 - [c73]Xuan Zhang, Zhuoran Song, Xing Li, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang:
HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model. ICCD 2023: 375-382 - 2022
- [c68]Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang:
EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks. DAC 2022: 259-264 - [i13]Zhuoran Song, Yihong Xu, Zhezhi He, Li Jiang, Naifeng Jing, Xiaoyao Liang:
CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity Prediction. CoRR abs/2203.04570 (2022) - [i12]Zhuoran Song, Yihong Xu, Han Li, Naifeng Jing, Xiaoyao Liang, Li Jiang:
DNN Training Acceleration via Exploring GPGPU Friendly Sparsity. CoRR abs/2203.05705 (2022) - [i11]Yilong Zhao, Li Jiang, Mingyu Gao, Naifeng Jing, Chengyang Gu, Qidong Tang, Fangxin Liu, Tao Yang, Xiaoyao Liang:
RePAST: A ReRAM-based PIM Accelerator for Second-order Training of DNN. CoRR abs/2210.15255 (2022) - 2021
- [j17]Zhuoran Song, Yanan Sun, Lerong Chen, Tianjian Li, Naifeng Jing, Xiaoyao Liang, Li Jiang:
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 129-142 (2021) - [c53]Yilong Zhao, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Re2PIM: A Reconfigurable ReRAM-Based PIM Design for Variable-Sized Vector-Matrix Multiplication. ACM Great Lakes Symposium on VLSI 2021: 15-20 - [c45]Feiyang Wu, Zhuoran Song, Jing Ke, Li Jiang, Naifeng Jing, Xiaoyao Liang:
PIPArch: Programmable Image Processing Architecture Using Sliding Array. ISPA/BDCloud/SocialCom/SustainCom 2021: 73-80 - [i10]Fangxin Liu, Wenbo Zhao, Yilong Zhao, Zongwu Wang, Tao Yang, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang:
SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network. CoRR abs/2103.01705 (2021) - 2020
- [c42]Zhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing:
GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores. DAC 2020: 1-6 - [c40]Tao Yang, Yunkun Liao, Jianping Shi, Yun Liang, Naifeng Jing, Li Jiang:
A Winograd-Based CNN Accelerator with a Fine-Grained Regular Sparsity Pattern. FPL 2020: 254-261 - [c38]Zhuoran Song, Bangqi Fu, Feiyang Wu, Zhaoming Jiang, Li Jiang, Naifeng Jing, Xiaoyao Liang:
DRQ: Dynamic Region-based Quantization for Deep Neural Network Acceleration. ISCA 2020: 1010-1021 - 2019
- [j12]Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, Li Jiang:
Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs 66-II(5): 753-757 (2019) - [j11]Li Jiang, Zhuoran Song, Haiyue Song, Chengwen Xu, Qiang Xu, Naifeng Jing, Weifeng Zhang, Xiaoyao Liang:
Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method. ACM Trans. Design Autom. Electr. Syst. 24(6): 59:1-59:25 (2019) - [c36]Houxiang Ji, Li Jiang, Tianjian Li, Naifeng Jing, Jing Ke, Xiaoyao Liang:
HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing. ASP-DAC 2019: 249-254 - [c35]Jianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing:
A sharing-aware L1.5D cache for data reuse in GPGPUs. ASP-DAC 2019: 388-393 - 2018
- [j10]Li Jiang, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang:
CNFET-Based High Throughput SIMD Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1331-1344 (2018) - [j8]Jianfei Wang, Qin Wang, Li Jiang, Chao Li, Xiaoyao Liang, Naifeng Jing:
IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs. IEEE Trans. Parallel Distributed Syst. 29(3): 586-599 (2018) - [c29]Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang:
A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only). FPGA 2018: 286 - [c28]Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang:
AXNet: approximate computing using an end-to-end trainable neural network. ICCAD 2018: 11:1-11:8 - [c27]Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximators. ICCAD 2018: 50 - [i2]Zhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang:
AXNet: ApproXimate computing using an end-to-end trainable neural network. CoRR abs/1807.10458 (2018) - [i1]Haiyue Song, Chengwen Xu, Qiang Xu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Invocation-driven Neural Approximate Computing with a Multiclass-Classifier and Multiple Approximators. CoRR abs/1810.08379 (2018) - 2017
- [j7]Jianfei Wang, Fengfeng Fan, Li Jiang, Xiaoyao Liang, Naifeng Jing:
Incorporating selective victim cache into GPGPU for high-performance computing. Concurr. Comput. Pract. Exp. 29(24) (2017) - [j6]Naifeng Jing, Shunning Jiang, Shuang Chen, Jingjie Zhang, Li Jiang, Chao Li, Xiaoyao Liang:
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 520-533 (2017) - [c26]Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique. DAC 2017: 38:1-38:6 - [c25]Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, Li Jiang:
On Quality Trade-off Control for Approximate Computing Using Iterative Training. DAC 2017: 52:1-52:6 - 2016
- [j5]Naifeng Jing, Li Jiang, Tao Zhang, Chao Li, Fengfeng Fan, Xiaoyao Liang:
Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs. IEEE Trans. Computers 65(1): 122-135 (2016) - [j4]Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang:
A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1192-1205 (2016) - [c22]Tianjian Li, Li Jiang, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang:
CNFET-based high throughput register file architecture. ICCD 2016: 662-669 - [c21]Fengfeng Fan, Jianfei Wang, Li Jiang, Xiaoyao Liang, Naifeng Jing:
Applying Victim Cache in High Performance GPGPU Computing. ISPDC 2016: 24-29 - [c19]Naifeng Jing, Jianfei Wang, Fengfeng Fan, Wenkang Yu, Li Jiang, Chao Li, Xiaoyao Liang:
Cache-emulated register file: An integrated on-chip memory architecture for high performance GPGPUs. MICRO 2016: 14:1-14:12 - 2015
- [c17]Feng Xie, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang:
Jump test for metallic CNTs in CNFET-based SRAM. DAC 2015: 16:1-16:6 - [c14]Naifeng Jing, Shuang Chen, Shunning Jiang, Li Jiang, Chao Li, Xiaoyao Liang:
Bank stealing for conflict mitigation in GPGPU Register File. ISLPED 2015: 55-60 - [c13]Li Jiang, Pu Pang, Naifeng Jing, Sung Kyu Lim, Xiaoyao Liang, Qiang Xu:
On diagnosable and tunable 3D clock network design for lifetime reliability enhancement. ITC 2015: 1-10 - [c9]Chen Wang, Li Jiang, Shiyan Hu, Tianjian Li, Xiaoyao Liang, Naifeng Jing, Weikang Qian:
Timing-driven placement for carbon nanotube circuits. SoCC 2015: 362-367
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last updated on 2024-09-21 02:34 CEST by the dblp team
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