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ORCIDRan Wang 0002
- > Home > Persons > Ran Wang 0002
Publications
- 2018
[j10]Shengcheng Wang
, Ran Wang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling. ACM Trans. Design Autom. Electr. Syst. 23(3): 35:1-35:25 (2018)- 2017
- [j9]Ran Wang, Krishnendu Chakrabarty:
Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits. IEEE Des. Test 34(5): 72-79 (2017) - [j8]Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty:
ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 1030-1042 (2017) - [j7]Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty:
Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(8): 1406-1419 (2017) - 2016
- [c11]Ran Wang, Krishnendu Chakrabarty:
Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and Solutions. ATS 2016: 74-79 - [c10]Shengcheng Wang, Ran Wang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICs. ATS 2016: 86-91 - [c9]Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty:
Pre-bond testing of the silicon interposer in 2.5D ICs. DATE 2016: 978-983 - [c8]Ran Wang, Krishnendu Chakrabarty:
A design-for-test solution for monolithic 3D integrated circuits. ETS 2016: 1-6 - [c7]Ran Wang, Sergej Deutsch, Mukesh Agrawal, Krishnendu Chakrabarty:
The hype, myths, and realities of testing 3D integrated circuits. ICCAD 2016: 58 - [c6]Ran Wang, Krishnendu Chakrabarty:
Testing of interposer-based 2.5D integrated circuits. ITC 2016: 1-10 - [c5]Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani:
A programmable method for low-power scan shift in SoC integrated circuits. VTS 2016: 1-6 - 2015
- [j6]Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik:
Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(1): 136-149 (2015) - [j5]Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik:
Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC. ACM Trans. Design Autom. Electr. Syst. 20(4): 58:1-58:24 (2015) - [c4]Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty:
ExTest scheduling for 2.5D system-on-chip integrated circuits. VTS 2015: 1-6 - 2014
- [j4]Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye:
Test and Design-for-Testability Solutions for 3D Integrated Circuits. Inf. Media Technol. 9(4): 386-403 (2014) - [j3]Krishnendu Chakrabarty, Mukesh Agrawal, Sergej Deutsch, Brandon Noia, Ran Wang, Fangming Ye:
Test and Design-for-Testability Solutions for 3D Integrated Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 7: 56-73 (2014) - [j2]Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty:
Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1231-1244 (2014) - [j1]Ran Wang, Krishnendu Chakrabarty, Bill Eklow:
Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1410-1423 (2014) - [c3]Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik:
Built-in self-test for interposer-based 2.5D ICs. ICCD 2014: 181-188 - [c2]Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik:
At-speed interconnect testing and test-path optimization for 2.5D ICs. VTS 2014: 1-6 - 2013
- [c1]Ran Wang, Krishnendu Chakrabarty, Bill Eklow:
Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs. Asian Test Symposium 2013: 147-152
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