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ORCIDISPD 2026: Bonn, Germany
- Stephan Held, Rickard Ewetz, Tung-Chieh Chen, Gracieli Posser:
Proceedings of the 2026 International Symposium on Physical Design, ISPD 2026, BonnGermany, March 15-18, 2026. ACM 2026, ISBN 979-8-4007-2314-8
Session 1: Opening Session and First Keynote
- Leon Stok:
Chip Design in the Era of AI & Quantum: From Idea to IC, are we there yet? 1
Session 2: Session on 3D IC Placement & Planning
- Cheng-Xun Song, Minh Anh Phan, Sheng-Tan Huang, Shao-Yun Fang, Tung-Chieh Chen, Kai-Shun Hu, Cindy Chin-Fang Shen:
Technology-Aware 3D Placement with ILP-Based Region Planning for Soft Modules. 2-10 - Zixian Yang, Shanyi Li, Leilei Jin, Tsung-Yi Ho, Chien-Nan Jimmy Liu:
IDDA-3D: Inter-Die Delay Aware Timing-Driven Placement on Face-to-Face Bonded 3D ICs. 11-19 - Siyuan Miao, Lingkang Zhu, Xiangqiao Meng, Wenkai Yang, Chengyu Zhu, Chen Wu, Lei He:
Multi-Level Interconnect Planning for Signal-Power-Thermal Integrity in 2.5D/3D Integration. 20-28
Session 3: Routing for Photonics and Advanced Packaging
- Hongjian Zhou, Haoyu Yang, Nicholas Gangi, Bowen Liu, Meng Zhang, Haoxing Ren, Xu Wang, Rena Huang, Jiaqi Gu:
LiDAR 3.0: Photonics-Aware Planning-Guided Automated Electrical Routing for Large-Scale Active Photonic Integrated Circuits. 29-37 - Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
Invited: Navigating the Frontier of Optimality and Complexity: Advanced Design Automation for Wavelength-Routed ONoCs. 38-45 - Hsin-Tzu Chang, Iris Hui-Ru Jiang, Hua-Yu Chang, Chun-Hao Lai:
Any-Angle Die-to-Die Routing for Advanced Packages with Asymmetric Pin Row Structures, Via Constraints, and Shielding-Aware Reservation. 46-54
Session 4: Placement and Global Routing
- Liang Xiao, Qinkai Duan, Leilei Jin, Jinwei Liu, Tsung-Yi Ho, Evangeline F. Y. Young, Martin D. F. Wong:
Gradient-Guided RC Weighting for Timing-Driven Global Routing. 55-63 - Zhili Xiong, Yi-Chen Lu, David Z. Pan, Haoxing Ren:
GrandPlan: Differentiable, Simultaneous Top-Level Floorplanning and Partition-Level Cell Placement for Large-Scale IP-Cores. 64-72 - Jens Vygen:
Invited: BonnRoute: Classic Routing Algorithms with Recent Advances. 73-74
Session 5: Advanced Cell and Transistor-Level Design
- Meng-Yu Shih, Ting Xin Lin, Yih-Lang Li:
A Graph-Based Approach for Optimizing Pin Access in Nanosheet FET Standard Cell Library Synthesis. 75-82 - Chen-Hao Hsu, David Z. Pan:
TransOpt: A Scalable Transistor-Level Placement and Routing Optimization Framework Beyond Standard Cells. 83-91 - Donghao Fang, Hailiang Hu, Wuxi Li, Jiang Hu:
A New Approach to Performance-Driven Analog IC Placement. 92-100 - Helena Krupnova:
Physical Synthesis/layout Issues Specific to FPGA-based Emulation. 101-108
Session 6: Second Keynote
- Thomas Stammler:
How Optical Lithography Enables the Digital Age. 109
Session 7: Panel: Agentic AI
- Thomas Andersen:
Invited: Agentic Chip Design from Spec2GDS - Faster and Better than a Human Expert? 110-111 - Yuhan Qin, Yuan Pu, Tairu Qiu, Zhuolun He, Bei Yu:
Invited: Infusing EDA Knowledge into LLM Systems: An Information-Source Perspective. 112-120 - Chia-Tung Ho, Jing Gong, Haoyu Yang, Abhishek B. Akkur, Haoxing Ren:
Invited: Polymath: Self-Improving Hierarchical Workflow for Multi-Domain Problem Solving. 121-130 - Ankur Gupta:
Invited: Breaking through Chip Design Barriers with AI-powered Physical Design Methodologies. 131-132 - Amur Ghose, Andrew B. Kahng, Sayak Kundu, Bodhisatta Pramanik:
Invited: Agentic AI for Physical Design R&D: Status and Prospects. 133-141
Session 8: Third Keynote
- Prith Banerjee:
Use of AI/ML in Electronic Design Automation and Engineering Simulation. 142-143
Session 9: AI and LLMs in Physical Design
- Runzhi Wang, Jingyu Pan, Yiran Chen, Jiang Hu:
AstroTune: AST-Assisted LLM Retrieval for Cross-Stage Design Flow Parameter Tuner. 144-152 - Shixin Chen, Hengyuan Zhang, Jianwang Zhai, Bei Yu:
CHASE: A CHiplet Architecture Simulation and Exploration Framework with Decoupled Multi-Fidelity Optimization. 153-161 - Ilhami H. Torunoglu:
Invited: A Bidirectional EDA Flow in VLSI Design Using Ontology and Knowledge Graph. 162
Session 10: Advanced Synthesis: From Classical to Quantum Architectures
- David G. Chinnery:
Invited: Improving Runtime Scaling in the EDA Flow for Designs with Millions of Gates. 163-171 - Will Reece:
Invited: Challenges and Opportunities in Advanced-node Design Closure. 172 - Tung-Yeh Wu, Ting-Chi Wang:
An Improved Ion-Shuttling Approach for QCCD Architectures. 173-181 - Ching-Yao Huang, Wai-Kei Mak:
Timing-Aware End-to-End Circuit Compilation Framework for Modular Quantum Systems. 182-190
Session 11: Reliability and Electromigration
- Sachin S. Sapatnekar:
Invited: Toward Accurate, Large-scale Electromigration Analysis and Optimization in Integrated Systems. 191-199 - Shanthi Siemes:
Invited: Electromigration Avoidance Strategies in Infineon. 200 - Ingo Kühn, Ivan Valentinov Petkov:
Invited: Addressing Electromigration Challenges in 3D Integrated Circuit (3DIC) Wafer-On-Wafer Technology: EM analysis in 3DIC - status and challenges. 201-202
Session 12: Automotive and Analog
- Klaus Heinrich, Pietro Buccella:
Invited: Substrate Netlist Extraction in Analog Design. 203-204 - Göran Jerke, Thomas Burdick, Vinko Marolt, Peter Herth, Andrew Beckett:
Invited: Novel Concepts to Improve Custom Layout Automation Capabilities. 205-213 - Aida Todri-Sanial:
Invited: Analog Computation with Oscillatory Neural Networks. 214-215 - Benjamin Prautsch, Uwe Eichler:
Invited: Analog IC Design Automation - More than a Technical Challenge. 216-217
Session 13: Lifetime Achievement Session
- Jürgen Scheible:
Invited: A History of Influences. 218-219 - Andrew B. Kahng:
Invited: The Many PD Faces of Professor Jens Lienig. 220-225 - Johann Knechtel, Susann Rothe, Robert Fischbach, Matthias Thiele, Tilo Meister, Andreas Krinke:
Invited: From Evolutionary Algorithms to Analog Design, Electromigration, 3D Integration, and Beyond: On Jens Lienig's Contributions to Advance Physical Design. 226-235 - Jens Lienig:
Invited: Layout Design Automation: From Academia to Industry and Back. 236
Session 14: Fourth Keynote
- Louis K. Scheffer:
Studying the Brain from the Perspective of EE. 237
Session 15: Benchmarking for EDA
- Rahul Rana, Tejas Bachhav, Aniruddha Dhumal, Ashutosh Pareek, Riya Sara Angel Korrapolu, Sathya Sai Ram Prabhala, Dishant Bhatnagar, Patrick H. Madden:
Invited: Benchmarker: A Web-Based System for Tracking Experimental Results. 238-244 - Liwen Jiang, Andrew B. Kahng, Zhiang Wang, Zhiyu Zheng:
Invited: Toward Sustainable and Transparent Benchmarking for Academic Physical Design Research. 245-253 - Sebastian Schlag, Tobias Heuer, Christian Schulz:
Invited: Modern Hypergraph Partitioning: KaHyPar, Mt-KaHyPar, and Beyond. 254-255
Session 16: Contest Results and Closing Remarks
- Andrew B. Kahng, Seokhyeong Kang, Sayak Kundu, Yiting Liu, Davit Markarian, Seonghyeon Park, Zhiang Wang:
Invited: Post-Placement Buffering and Sizing Contest. 256-262
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