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ORCIDJianwang Zhai
Person information
- unicode name: 翟建旺
- affiliation: Beijing University of Posts and Telecommunications (BUPT), School of Integrated Circuits, Beijing, China
- affiliation (former, pHd 2023): Tsinghua University, Beijing, China
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2020 – today
- 2025
[j5]Kang Yang
, Jianwang Zhai, Liuyu Xiang, Zixi Huang, Dan Wu, Yida Wang, Kang Zhao, Ming Lei, Zhaofeng He:
DrlGoFPGA: FPGA Global Placement Considering Input-Output Buffer Based on Deep Reinforcement Learning and Gradient Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 72(11): 7016-7029 (2025)- [c21]Guande Dong, Jianwang Zhai, Hongtao Cheng, Xiao Yang, Chuan Shi, Kang Zhao:
PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis. ASP-DAC 2025: 65-71 - [c20]Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu:
The Survey of 2.5D Integrated Architecture: An EDA perspective. ASP-DAC 2025: 285-293 - [c19]Zirui Li, Kanglin Tian, Jianwang Zhai, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu, Kang Zhao:
FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs. ASP-DAC 2025: 886-892 - [c18]Feng Guo, Yueyue Xi, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Chuan Shi:
IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction. DAC 2025: 1-7 - [c17]Xinya Luan, Zhe Lin, Kai Shi, Jianwang Zhai, Kang Zhao:
HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design. DAC 2025: 1-7 - [c16]Kai Shi, Zhe Lin, Xinya Luan, Jianwang Zhai, Kang Zhao:
VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration. DAC 2025: 1-7 - [c15]Yuyang Ye, Mingwei He, Lizheng Ren, Jianwang Zhai, Tinghuan Chen, Jun Yang, Longxing Shi:
Truly Pre-Routing Timing Prediction via Considering Power Delivery Network. DAC 2025: 1-7 - [c14]Feng Guo, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Bei Yu, Chuan Shi:
IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning. DATE 2025: 1-7 - [c13]Jiawei Liu, Zhiyan Liu, Xun He, Jianwang Zhai, Zhengyuan Shi, Qiang Xu, Bei Yu, Chuan Shi:
WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction. DATE 2025: 1-7 - [c12]Mingyu Zhao, Jiawei Liu, Jianwang Zhai, Chuan Shi:
MILS: Modality Interaction Driven Learning for Logic Synthesis. ACM Great Lakes Symposium on VLSI 2025: 64-70 - [c11]Zichao Ling, Lin Li, Yi Huang, Yixin Xuan, Jianwang Zhai, Kang Zhao:
AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design. ACM Great Lakes Symposium on VLSI 2025: 879-885 - [c10]Shan Shen, Shenglu Hua, Jiajun Zou, Jiawei Liu, Jianwang Zhai, Chuan Shi, Wenjian Yu:
Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits. ICCAD 2025: 1-9 - [c9]Zixuan Li, Kanglin Tian, Jianwang Zhai, Zirui Li, Kang Zhao:
HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules. ISCAS 2025: 1-5 - [i3]Shan Shen, Shenglu Hua, Jiajun Zou, Jiawei Liu, Jianwang Zhai, Chuan Shi, Wenjian Yu:
Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits. CoRR abs/2507.06535 (2025) - [i2]Shuao Jia, Zichao Ling, Chen Bai, Kang Zhao, Jianwang Zhai:
FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators. CoRR abs/2511.22348 (2025) - 2024
- [j4]Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration. ACM Trans. Design Autom. Electr. Syst. 29(1): 20:1-20:23 (2024) - [c8]Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. AAAI 2024: 12-20 - [c7]Jingyu Jia, Jianwang Zhai, Kang Zhao:
Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model. DATE 2024: 1-2 - [c6]Feng Guo, Jiawei Liu, Jianwang Zhai, Jingyu Jia, Kang Zhao, Chuan Shi:
PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing. ACM Great Lakes Symposium on VLSI 2024: 452-458 - [c5]Jiawei Liu, Jianwang Zhai, Mingyu Zhao, Zhe Lin, Bei Yu, Chuan Shi:
PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network. ICCAD 2024: 185:1-185:9 - [c4]Zirui Li, Jianwang Zhai, Zixuan Li, Zhongdong Qi, Kang Zhao:
Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing. ISCAS 2024: 1-5 - [i1]Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu:
The Survey of Chiplet-based Integrated Architecture: An EDA perspective. CoRR abs/2411.04410 (2024) - 2023
- [j3]Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu:
McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 243-256 (2023) - [j2]Jianwang Zhai, Yici Cai:
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1727-1739 (2023) - [c3]Jianwang Zhai, Yici Cai, Bei Yu:
Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. ASP-DAC 2023: 302-307 - 2021
- [j1]Jianwang Zhai, Yici Cai, Qiang Zhou:
Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1571-1575 (2021) - [c2]Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. ICCAD 2021: 1-9 - [c1]Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu:
McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. ICCAD 2021: 1-9
Coauthor Index
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