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ORCIDICICDT 2016: Ho Chi Minh, Vietnam
- International Conference on IC Design and Technology, ICICDT 2016, Ho Chi Minh, Vietnam, June 27-29, 2016. IEEE 2016, ISBN 978-1-5090-0827-8
- Chi Lan Phuong Nguyen, My Phi Ngoc Nguyen, Hung Van Cao, Katsushige Matsubara, Keisuke Matsumoto, Seiji Mochizuki, Kenichi Iwata:
71% Reducing the memory bandwidth requirement for a multi-standard video codec by lossless compression of video using a combination of 2D-DPCM and Variable Length Coding. 1-5 - Dinh Thuc Nguyen:
A 200-mA CMOS low-dropout regulator with high current-efficient and transient-response improvement. 1-4 - Benqing Guo, Jun Chen, Haiyan Jin:
A 4.2 mW 3.1 dBm IIP3 LNA in 0.13 μm CMOS for wideband communications. 1-4 - Duy Dang, Thang Tran Quoc, Kien Nguyen Van:
A 65-nm CMOS high-efficiency PWM/PFM Buck Converter with Bypass mode for Transceiver applications. 1-4 - Van-Lan Dao
, Van-Phuc Hoang, Anh-Thai Nguyen, Quy-Minh Le:
A compact, low power AES core on 180nm CMOS process. 1-5 - Shanthi Sudalaiyandi, Gilles Masson, Mykhailo Zarudniev:
A digitally controlled oscillator suitable for on-chip integration in 65 nm CMOS. 1-4 - Xuan-Thuan Nguyen, Hong-Thu Nguyen, Cong-Kha Pham:
A high-throughput and low-power design for bitmap indexing on 65-nm SOTB CMOS process. 1-4 - Tsung-Yi Tsai, Yan-You Chou, Chua-Chin Wang:
A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above. 1-4 - Michail Noltsis, Pieter Weckx, Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris:
Accuracy of Quasi-Monte Carlo technique in failure probability estimations. 1-4 - Nguyen Hung Quan, Duong Hai Dang Linh, Trinh Viet Quang, Hoang Minh The Nghi, Nguyen Phu Quoc, Tran Kien Cuong, Hoang Xuan Hoa:
An all-in-one debugger of 8-bit microcontroller with high transfer speed. 1-4 - Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi:
An area compact soft error resident circuit for FPGA. 1-4 - Vincenzo Stornelli, Leonardo Pantoli, Giorgio Leuzzi, Alfiero Leoni:
An assessment on low-voltage low-power integrated single transistor active inductor design for RF filter applications. 1-4 - Wu-Chang Chang, Po-Ching Wu, Cheng-Hao Po, Chun-Fu Lin, Ching-Yuan Lin, Chih-Hsin Chen:
An ultra low power operated logic NVM for passive UHF RFID tag applications. 1-4 - Phong Nguyen Thanh, Khanh Nguyen Tuan, Xuan Mai Dong:
A 100-μW wake-up receiver for UHF transceiver. 1-4 - Nadine Collaert, AliReza Alian, Hiroaki Arimura, Geert Boccardi, Geert Eneman, Jacopo Franco, Tsvetan Ivanov, Dennis Lin, Jérôme Mitard, S. Ramesh, R. Rooyackers, Marc Schaekers, A. Sibaya-Hernandez, S. Sioncke, Quentin Smets, Abhitosh Vais, A. Vandooren, Anabela Veloso, Anne S. Verhulst, Devin Verreck, Niamh Waldron, Amey Walke, Liesbeth Witters, H. Yu, X. Zhou, Aaron Voon-Yew Thean:
Beyond-Si materials and devices for more Moore and more than Moore applications. 1-5 - Masanori Iwata, Kenji Miyake, Nobuyoshi Yamauchi, Junko Kazusa:
Blue GaN based LED fabrication using hybrid process of the minimal photolithography system and MOCVD. 1-4 - Manh-Cuong Nguyen, An Hoang-Thuy Nguyen, Jae-Won Choi, Soo-Yeun Han, Jung-Yeon Kim, Rino Choi, Changhwan Choi:
Characterization of high pressure hydrogen annealing effect on polysilicon channel field effect transistors using isothermal deep level trap spectroscopy. 1-4 - Jin Kawakita, Toyohiro Chikyow:
Conductive polymer/metal composite for flexible interconnect. 1-4 - Sommawan Khumpuang, Shiro Hara:
Development of fundamental manufacturing processes for minimal fab. 1-4 - Nguyen Dang Chien, Nguyen Thi Thu, Chun-Hsing Shih, Luu The Vinh:
Different scalabilities of N- and P-type tunnel field-effect transistors with Si/SiGe heterojunctions. 1-4 - Minh-Huan Vo:
Dynamic CMOS-rectifying memristor multiplier architecture for power reduction. 1-4 - Jian-Hao Wang, Yin-Nien Chen, Pin Su, Ching-Te Chuang:
Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling. 1-4 - D. H. Triyoso, Rick Carter, J. Kluth, K. Hempel, M. Gribelyuk, L. Kang, A. Kumar, B. Mulfinger, P. Javorka, K. Punchihewa, A. Child, T. McArdle, J. Holt, S. Straub, R. Sporer, P. Chen:
Extending HKMG scaling on CMOS with FDSOI: Advantages and integration challenges. 1-4 - Nana Sutisna, Reina Hongyo, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi:
Fast design exploration with unified HW/SW co-verification framework for high throughput wireless communication system. 1-4 - Rick Shih-Jye Shen, Hsin-Ming Chen, Meng-Yi Wu:
Highly reliable anti-fuse technology in sub-16nm technologies for security applications. 1-4 - Jun Ma, Elison Matioli:
Improved electrical and thermal performances in nanostructured GaN devices. 1-4 - Wenke Weinreich, Konrad Seidel, Patrick Polakowski, Maximilian Drescher, A. Gummenscheimer, Mark G. Nolan, L. Cheng, D. H. Triyoso:
La-doped ZrO2 based BEoL decoupling capacitors. 1-4 - Pengpeng Ren, Runsheng Wang, Ru Huang:
Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life. 1-3 - Zong-You Hou, Teng-Wei Huang, Chua-Chin Wang:
On-chip accurate primary-side output current estimator for flyback LED driver control. 1-4 - Toan Thanh Dao:
Organic complementary amplifier circuits with mixed dielectrics for large-area active collision detection sensors. 1-4 - Michihiro Inoue, Fumito Imura, Arami Saruwatari, Shiro Hara:
Packaging in minimal fab: An integrated semiconductor line from wafer process to packaging process. 1-3 - Seongbo Shim, Woohyun Chung, Youngsoo Shin:
Placement optimization for MP-DSAL compliant layout. 1-4 - Philippe Galy, S. Athanasiou:
Preliminary results on TFET - Gated diode in thin silicon film for IO design & ESD protection in 28nm UTBB FD-SOI CMOS technology. 1-4 - Claire Fenouillet-Béranger, Perrine Batude, Laurent Brunet, Vincent Mazzocchi, Cao-Minh Vincent Lu, Fabien Deprat, Jessy Micout, M.-P. Samson, Bernard Previtali, Paul Besombes, Nils Rambal, François Andrieu, Olivier Billoint, Melanie Brocard, Sébastien Thuries, Gerald Cibrario, Maud Vinet:
Recent advances in 3D VLSI integration. 1-4 - Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin:
Register grouping for synthesis of clock gating logic. 1-4 - Khanh Nguyen Quoc, Dong Bach Tuan, Toan Le Duc:
The design of a phase compensator for the CIC decimation filter. 1-4 - Nhan Do:
Scaling of split-gate flash memory and its adoption in modern embedded non-volatile applications. 1-4 - Khanh N. Dang, Yuichi Okuyama, Abderazek Ben Abdallah:
Soft-error resilient Network-on-Chip for safety-critical applications. 1-4 - Ko-Chi Kuo:
The implementation of HomePlug AV system. 1-4 - Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran:
Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications. 1-4
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