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2020 – today
- 2025
[c57]Anirudh Seshadri, Eric Rotenberg
:
Delinquent Loop Pre-execution Using Predicated Helper Threads. HPCA 2025: 44-58- [c56]Debpratim Adak, Huiyang Zhou, Eric Rotenberg, Amro Awad:
SpecMPK: Efficient In-Process Isolation with Speculative and Secure Permission Update Instruction. HPCA 2025: 394-408 - 2021
- [c55]Chanchal Kumar, Anirudh Seshadri, Aayush Chaudhary, Shubham Bhawalkar, Rohit Singh, Eric Rotenberg:
Post-Fabrication Microarchitecture. MICRO 2021: 1270-1281 - 2020
- [j11]Chanchal Kumar, Aayush Chaudhary, Shubham Bhawalkar, Utkarsh Mathur, Saransh Jain, Adith Vastrad, Eric Rotenberg:
Post-Silicon Microarchitecture. IEEE Comput. Archit. Lett. 19(1): 26-29 (2020) - [c54]Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Eric Rotenberg:
Slipstream Processors Revisited: Exploiting Branch Sets. ISCA 2020: 105-117
2010 – 2019
- 2017
- [c53]Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor. ICCD 2017: 145-152 - [c52]Sungkwan Ku, Elliott Forbes, Rangeen Basu Roy Chowdhury, Eric Rotenberg:
A case for standard-cell based RAMs in highly-ported superscalar processor structures. ISQED 2017: 131-137 - 2016
- [c51]Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
Physical design of a 3D-stacked heterogeneous multi-core processor. 3DIC 2016: 1-5 - [c50]Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Eric Rotenberg:
AnyCore-1: A comprehensively adaptive 4-way superscalar processor. Hot Chips Symposium 2016: 1 - [c49]Elliott Forbes, Eric Rotenberg:
Fast register consolidation and migration for heterogeneous multi-core processors. ICCD 2016: 1-8 - [c48]Rangeen Basu Roy Chowdhury, Anil K. Kannepalli, Sungkwan Ku, Eric Rotenberg:
AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores. ISPASS 2016: 214-224 - 2015
- [j10]Rami Sheikh, James Tuck, Eric Rotenberg:
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching. IEEE Trans. Computers 64(8): 2182-2203 (2015) - [c47]Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa:
Computing in 3D. 3DIC 2015: TS6.1.1-TS6.1.2 - [c46]Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Steve Lipa:
Computing in 3D. CICC 2015: 1-6 - [c45]Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon H. Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor. Hot Chips Symposium 2015: 1 - 2014
- [c44]Paul D. Franzon, Eric Rotenberg, James Tuck, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, Steve Lipa, Chao Li, Jong Beom Park, Joshua Schabel:
3D-enabled customizable embedded computer (3DECC). 3DIC 2014: 1-3 - [c43]Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo:
Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. ASP-DAC 2014: 400-405 - [c42]Elliott Forbes, Niket Kumar Choudhary, Brandon H. Dwiel, Eric Rotenberg:
Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores. ICCD 2014: 408-415 - 2013
- [c41]Nyunyi M. Tshibangu, Paul D. Franzon, Eric Rotenberg, William Rhett Davis:
Design of controller for L2 cache mapped in Tezzaron stacked DRAM. 3DIC 2013: 1-4 - [c40]Sandeep Navada, Niket K. Choudhary, Salil V. Wadhavkar, Eric Rotenberg:
A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors. PACT 2013: 133-144 - [c39]Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon:
Rationale for a 3D heterogeneous multi-core processor. ICCD 2013: 154-168 - [c38]Shivam Priyadarshi, Niket K. Choudhary, Brandon H. Dwiel, Ankita Upreti, Eric Rotenberg, William Rhett Davis, Paul D. Franzon:
Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors. ISQED 2013: 1-7 - 2012
- [j9]Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg:
FabScalar: Automating Superscalar Core Design. IEEE Micro 32(3): 48-59 (2012) - [c37]Brandon H. Dwiel, Niket Kumar Choudhary, Eric Rotenberg:
FPGA modeling of diverse superscalar processors. ISPASS 2012: 188-199 - [c36]Rami Sheikh, James Tuck, Eric Rotenberg:
Control-Flow Decoupling. MICRO 2012: 329-340 - [c35]Niket K. Choudhary, Brandon H. Dwiel, Eric Rotenberg:
A physical design study of fabscalar-generated superscalar cores. VLSI-SoC 2012: 165-170 - 2011
- [c34]Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, Hashem Hashemi Najaf-abadi, Eric Rotenberg:
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. ISCA 2011: 11-22 - 2010
- [c33]Sandeep Navada, Niket Kumar Choudhary, Eric Rotenberg:
Criticality-driven superscalar design space exploration. PACT 2010: 261-272 - [c32]Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg:
EXACT: explicit dynamic-branch prediction with active updates. Conf. Computing Frontiers 2010: 165-176
2000 – 2009
- 2009
- [c31]Hashem Hashemi Najaf-abadi, Niket Kumar Choudhary, Eric Rotenberg:
Core-Selectability in Chip Multiprocessors. PACT 2009: 113-122 - [c30]Hashem Hashemi Najaf-abadi, Eric Rotenberg:
Architectural Contesting. HPCA 2009: 189-200 - [c29]Hashem Hashemi Najaf-abadi, Eric Rotenberg:
The importance of accurate task arrival characterization in the design of processing cores. IISWC 2009: 75-85 - 2008
- [c28]Vimal K. Reddy, Eric Rotenberg:
Coverage of a microarchitecture-level fault check regimen in a superscalar processor. DSN 2008: 1-10 - [c27]Hashem Hashemi Najaf-abadi, Eric Rotenberg:
Configurational Workload Characterization. ISPASS 2008: 147-156 - 2007
- [j8]Hashem Hashemi Najaf-abadi, Eric Rotenberg:
Architectural contesting: exposing and exploiting temperamental behavior. SIGARCH Comput. Archit. News 35(3): 28-35 (2007) - [j7]Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg:
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. IEEE Trans. Computers 56(2): 147-160 (2007) - [c26]Vimal K. Reddy, Eric Rotenberg:
Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. DSN 2007: 307-316 - [c25]Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary:
Transparent control independence (TCI). ISCA 2007: 448-459 - 2006
- [j6]Aravindh Anantaraman, Eric Rotenberg:
Non-uniform program analysis & repeatable execution constraints: exploiting out-of-order processors in real-time systems. SIGBED Rev. 3(1): 17-22 (2006) - [j5]Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg:
FAST: Frequency-aware static timing analysis. ACM Trans. Embed. Comput. Syst. 5(1): 200-224 (2006) - [c24]Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy:
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. ASPLOS 2006: 83-94 - [c23]Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg:
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM. HPCA 2006: 155-165 - [c22]Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi:
Assertion-Based Microarchitecture Design for Improved Reliability. ICCD 2006: 362-369 - [c21]Eric Rotenberg, Ravi V. Venkatesan:
The State of ZettaRAM. Nano-Net 2006: 1-5 - 2005
- [c20]Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg:
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing. CASES 2005: 213-224 - [c19]Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg:
Tapping ZettaRAMTM for Low-Power Memory Systems. HPCA 2005: 83-94 - 2004
- [j4]Jinson Koppanalil, Eric Rotenberg:
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. IEEE Trans. Computers 53(4): 399-413 (2004) - [c18]Ali El-Haj-Mahmoud, Eric Rotenberg:
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. CASES 2004: 2-13 - [c17]Aravindh Anantaraman, Kiran Seth, Eric Rotenberg, Frank Mueller:
Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA). RTSS 2004: 114-125 - 2003
- [j3]Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte:
Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embed. Comput. Syst. 2(3): 347-372 (2003) - [c16]Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg:
Slipstream Execution Mode for CMP-Based Multiprocessors. HPCA 2003: 179-190 - [c15]Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller:
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. ISCA 2003: 350-361 - [c14]Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg:
FAST: Frequency-Aware Static Timing Analysis. RTSS 2003: 40-51 - 2002
- [c13]Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg:
A case for dynamic pipeline scaling. CASES 2002: 1-8 - [c12]Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan:
A Large, Fast Instruction Window for Tolerating Cache Misses. ISCA 2002: 59-70 - 2001
- [c11]Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte:
Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT 2001: 61-70 - [c10]Eric Rotenberg:
Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. MICRO 2001: 28-39 - 2000
- [j2]Eric Rotenberg, James E. Smith:
Control Independence in Trace Processors. J. Instr. Level Parallelism 2 (2000) - [c9]Karthik Sundaramoorthy, Zachary Purser, Eric Rotenberg:
Slipstream Processors: Improving both Performance and Fault Tolerance. ASPLOS 2000: 257-268 - [c8]Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg:
A study of slipstream processors. MICRO 2000: 269-280
1990 – 1999
- 1999
- [j1]Eric Rotenberg, Steve Bennett, James E. Smith:
A Trace Cache Microarchitecture and Evaluation. IEEE Trans. Computers 48(2): 111-120 (1999) - [c7]Eric Rotenberg:
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. FTCS 1999: 84-91 - [c6]Eric Rotenberg, Quinn Jacobson, James E. Smith:
A Study of Control Independence in Superscalar Processors. HPCA 1999: 115-124 - [c5]Eric Rotenberg, James E. Smith:
Control Independence in Trace Processors. MICRO 1999: 4-15 - 1997
- [c4]Quinn Jacobson, Eric Rotenberg, James E. Smith:
Path-Based Next Trace Prediction. MICRO 1997: 14-23 - [c3]Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith:
Trace Processors. MICRO 1997: 138-148 - 1996
- [c2]Eric Rotenberg, Steve Bennett, James E. Smith:
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. MICRO 1996: 24-35 - [c1]Erik Jacobsen, Eric Rotenberg, James E. Smith:
Assigning Confidence to Conditional Branch Predictions. MICRO 1996: 142-152
Coauthor Index
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