VLSI -SoC 2010:
Madrid, SpainKeynote
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conf/vlsi/NageswaranRDK10
Systems-On-Chip and Networks-on-Chip Design
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Andy Motten ,
Luc Claesen :
A binary adaptable window SoC architecture for a stereo vision based depth field processor.
25-30
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Prototyping, Verification and Modeling
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conf/vlsi/Abdel-KhalekB10 export record as
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Poster Session 1
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conf/vlsi/BattezzatiSVD10 export record as
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conf/vlsi/AghamirzaieRZN10 export record as
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Pramod Kumar Meher :
An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks.
91-95
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conf/vlsi/PoucheretBBTMR10 export record as
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Yngvar Berg :
Ultra low voltage and high speed CMOS flip-flop using floating-gates.
111-114
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Yngvar Berg :
Static ultra-low-voltage high-speed CMOS logic and latches.
115-118
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Analog and Mixed Signal IC Design
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conf/vlsi/KhereddineASMC10 export record as
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Digital Signal Processing and Image Processing IC Design
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Pramod Kumar Meher :
Novel input coding technique for high-precision LUT-based multiplication for DSP applications.
201-206
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Digital System Design and Architectures
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Yngvar Berg :
Novel ultra low-voltage and high speed domino CMOS logic.
225-228
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Circuits and Systems for New Applications
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conf/vlsi/ClaesenVLMNWRF10 export record as
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conf/vlsi/AbdelsalamWADI10 export record as
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Green Computing
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conf/vlsi/JimenezGKCCBBV10
Logic Synthesis, Testability and Design for Test
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conf/vlsi/JaccottetCAFM10 export record as
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Architectures for DSP and Video Processing Applications
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Maher Jridi ,
Ayman Alfalou :
A low-power, high-speed DCT architecture for image compression: Principle and implementation.
304-309
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conf/vlsi/HusemannMGSRL10 export record as
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Deep Submicron Design
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conf/vlsi/StanisavljevicSL10 export record as
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Manycore Architectures
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conf/vlsi/VentrouxSDBGB10
Low Power Circuit Design
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Hailong Jiao ,
Volkan Kursun :
Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits.
347-351
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Physical Design for 3D Integration and Communication Systems
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Tsung-Yi Ho ,
Sheng-Hung Liu :
Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization.
369-374
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New Architectures for Reconfigurable Systems-on-chip and Multiprocessor Systems-on-chip
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Chengmo Yang ,
Alex Orailoglu :
Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations.
396-401
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Ji Kong ,
Peilin Liu :
A novel reconfigurable scratchpad memory for audio applications on cost-effective SoC.
402-407
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