SoCC 2009:
Belfast,
Northern Ireland,
UK
Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings.
IEEE 2009, ISBN 978-1-4244-4940-8 
Plenary Session
Session WA1:
FPGA Design Methodologies
- Wayne Luk, José Gabriel de Figueiredo Coutinho, Timothy John Todman, Yuet Ming Lam, William G. Osborne, Kong Woei Susanto, Qiang Liu, W. S. Wong:
A high-level compilation toolchain for heterogeneous systems.
9-18
- Maurizio Tranchero, Leonardo Maria Reyneri:
A multi-level simulation approach in a Simulink-based design tool for FPGAs.
19-22
- Joseph M. Lancaster, Jeremy D. Buhler, Roger D. Chamberlain:
Efficient runtime performance monitoring of FPGA-based applications.
23-28
- Süleyman Sirri Demirsoy, Kellie Marks:
SoC framework for FPGA: A case study of LTE PUSCH receiver.
29-32
Session WA2 - PLL and Clocks
- Saiyu Ren, Ray Siferd:
Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS.
35-38
- Ping Lu, Danfeng Chen, Fan Ye, Junyan Ren:
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator.
39-42
- Nan Xing, Heesoo Song, Deog-Kyoon Jeong, Suhwan Kim:
A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines.
43-46
- Marta Blaszczyk, Richard A. Guinee:
Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generator.
47-50
- Chorng-Sii Hwang, Chun-Yung Cho, Chung-Chun Chen, Hen-Wai Tsao:
Dual-band CDR using a half-rate linear phase detector.
51-54
Session WA3 - Reconfigurable Architectures
Session WB1 - A/D Converters
Session WB2 - Embedded Systems,
Multi Core,
and Embedded Memory
- Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
Adaptive energy-aware latency-constrained DVFS policy for MPSoC.
89-92
- Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis:
A configurable length, Fused Multiply-Add floating point unit for a VLIW processor.
93-96
- Wei Han, Ying Yi, Xin Zhao, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan:
Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter.
97-100
- Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang:
Asymmetrical Write-assist for single-ended SRAM operation.
101-104
Session WB3 - Low-Power Circuits and Architectures
Session TA1 - Circuits for RF and Wireless
Session TA2 - NoC Power and Data Flow Optimization
Session TA3 - Design for Testability and Verification
Poster Session
Analog and Mixed Signals
RF and Wireless
Embedded Systems,
Multi Core,
and Embedded Memory
Low Power
Verification
Audio and Video Processing
Network on Chip and Interconnect
- Shufan Yang, Stephen B. Furber, Luis A. Plana:
Adaptive admission control on the SpiNNaker MPSoC.
243-246
- Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan:
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT.
251-254
- Xiaofei Guo, Shunting Lin, Wael Refai, Garrett S. Rose:
Non-overlapping transition encoding for global on-chip interconnect.
255-258
- Azeez Sanusi, Magdy A. Bayoumi:
Smart-flooding: A novel scheme for fault-tolerant NoCs.
259-262
System Level Design Methodology
Reconfigurable and Programmable Circuits and Systems,
FPGAs
NEMS/MEMS Devices
Session TB1 - Analog Circuit Techniques
Session TB2 - System Level Design for Manufacturing
Session TB3 - Data Processing Architectures
Session FA1 - Low-Power Design Methodologies and IP Cores
- Sohaib Majzoub, Resve Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward:
Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT.
357-360
- Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler:
Fast dynamic power estimation considering glitch filtering.
361-364
- Ashok Narasimhan, Ramalingam Sridhar:
Variation aware low power buffered interconnect design.
365-368
- Tom English, Maurice Keller, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, William P. Marnane:
A low-power pairing-based cryptographic accelerator for embedded security applications.
369-372
Session FA2 - NoC Design Tools and Digital Signal Processing
Session FB1 - System Level Architecture Exploration
- Moazzam Fareed Niazi, Khalid Latif, Hannu Tenhunen, Tiberiu Seceleanu:
A DSL for the SegBus platform.
393-398
- Sumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla:
Accurate power estimation of hardware co-processors using system level simulation.
399-402
- Maurizio Tranchero, Leonardo Maria Reyneri:
Generating interacting synchronous and asynchronous designs from simulink descriptions.
403-406
- Hari Kannan, Mihai Budiu, John D. Davis, Girish Venkataramani:
Tuning SoCs using the global dynamic critical path.
407-411
- Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, Christian Schlegel:
High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath.
412-415
Session FB2 - Imaging and Video Processing
- Hoyoung Chang, Soojin Kim, Seonyoung Lee, Kyeongsoon Cho:
High-performance architecture of H.264 integer-pixel motion estimation IP for real-time 1080HD video CODEC.
419-422
- Michael Guarisco, Hassan Rabah, Yves Berviller, Serge Weber, Said Belkouch:
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding.
423-426
- Norman Nolte, Sören Moch, Markus Kock, Peter Pirsch:
Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams.
427-431
- Yongseok Jin, Hyuk-Jae Lee:
Pixel-Parallel SPIHT for frame memory compression.
432-435
- Sang-Jin Lee, Kyung-Chang Park, Yeon-Ho Kim, Yun-ki Hong, Younggap You, Kyoung-Rok Cho, Tae Won Cho, Kamran Eshraghian:
System-on-System (SoS) architecture for 3-D secure imaging.
436-439
Tutorials
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