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ORCIDAshok Narasimhan
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2010 – 2019
- 2010
[j1]Ashok Narasimhan, Ramalingam Sridhar:
Variability Aware Low-Power Delay Optimal Buffer Insertion for Global Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3055-3063 (2010)
2000 – 2009
- 2009
- [c9]Ashok Narasimhan, Ramalingam Sridhar:
Variation aware low power buffered interconnect design. SoCC 2009: 365-368 - 2008
- [c8]Ashok Narasimhan, Ramalingam Sridhar:
A low power and low area active clock deskewing technique for sub-90nm technologies. SoCC 2008: 179-182 - 2007
- [c7]Ashok Narasimhan, Ramalingam Sridhar:
Impact of Variability on Clock Skew in H-tree Clock Networks. ISQED 2007: 458-466 - 2006
- [c6]Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar:
A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects. VLSI Design 2006: 491-494 - [c5]Prachee Sharma, Asheq Khan, Ashok Narasimhan, Ramalingam Sridhar, Satish K. Tripathi:
Energy Conservation in Sensor Networks through Selective Node Activation. WOWMOM 2006: 115-124 - 2005
- [c4]Ashok Narasimhan, Karthik Srinivasan, Ramalingam Sridhar:
A High-Performance Router Design for VDSM NoCs. SoCC 2005: 301-304 - [c3]Ashok Narasimhan, Shantanu Divekar, Praveen Elakkumanan, Ramalingam Sridhar:
A Low-Power Current-Mode Clock Distribution Scheme for Multi-GHz NoC-Based SoCs. VLSI Design 2005: 130-133 - [c2]Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar:
A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects. VLSI Design 2005: 634-639 - 2004
- [c1]Praveen Elakkumanan, Vishwanath Ananthakrishnan, Ashok Narasimhan, Ramalingam Sridhar:
Leakage aware SER reduction technique for UDSM logic circuits. SoCC 2004: 82-85
Coauthor Index
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