SBCCI 2005: Florianolpolis, Brazil

• Luca Benini:
  Advanced power management of SoC platforms. 1
  
• Paul L. Jespers:
  A design methodology for analogue CMOS circuits. 2
  
• John Sanguinetti:
  The process of higher level design. 3
  
• Abdelkarim Mercha:
  Technology and architecture for deep submicron RF CMOS technology. 4
  
• John Sanguinetti:
  High level design: the future is now. 5
  
• Luca Benini:
  Energy efficient NoC design. 6
  
• Paul L. Jespers:
  A survey of multistep A to D converters and error correction mechanisms. 7
  
• Armando G. da Silva Jr.:
  IC design requirements for automotive applications. 8
  

Networks-on-chip and IC design

• Armando Gomes, Edevaldo Pereira S. Júnior, Ivan Carlos Ribeiro do Nascimento:
  EMC-EMI optimized high speed CAN line driver. 9-14
  

Analog design and modeling

• Alfredo Arnaud, Rafaella Fiorelli, Carlos Galup-Montoro:
  On the design of very small transconductance OTAs with reduced input offset. 15-20
  
• Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eduardo Conrad Jr., Sergio Bampi:
  T-shaped association of transistors: modeling of multiple channel lengths and regular associations. 21-26
  
• E. P. Santana, N. R. Ferreira, Carlos Eduardo Trabuco Dórea, Ana Isabela Araújo Cunha:
  On the adequate transistor modeling for optimal design of CMOS OTA. 27-31
  
• Carlos Galup-Montoro, Márcio C. Schneider, Viriato C. Pahim:
  Fundamentals of next generation compact MOSFET models. 32-37
  

CAD methods and synthesis

• Renato Fernandes Hentschke, Jagannathan Narasimhan, David S. Kung:
  Improving run times by pruned application of synthesis transforms. 38-43
  
• Nikolay Rubanov:
  An efficient subcircuit recognition using the nonlinear graph matching. 44-49
  
• Bastian Knerr, Martin Holzer, Markus Rupp:
  Task sheduling for power optimisation of multi frequency synchronous data flow graphs. 50-55
  
• Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau:
  Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. 56-61
  

Test

• Egas Henes Neto, Ivandro Ribeiro, Michele G. Vieira, Gilson I. Wirth, Fernanda Lima Kastensmidt:
  Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic. 62-67
  
• Marcelo de Souza Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski:
  A constraint-based solution for on-line testing of processors embedded in real-time applications. 68-73
  
• Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante:
  Automatic generation of test sets for SBST of microprocessor IP cores. 74-79
  
• Carlos Arthur Lang Lisbôa, Erik Schüler, Luigi Carro:
  Going beyond TMR for protection against multiple faults. 80-85
  

Embedded systems

• Xiangrong Zhou, Peter Petrov:
  Arithmetic-based address translation for energy-efficient virtual memory support in low-power, real-time embedded systems. 86-91
  
• Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro:
  Exploiting Java through binary translation for low power embedded reconfigurable systems. 92-97
  
• Eduardo Tavares, Paulo Romero Martins Maciel, Arthur Bessa, Raimundo S. Barreto, Leonardo Barros, Meuse N. Oliveira Jr., Ricardo Massa Ferreira Lima:
  A time petri net based approach for embedded hard real-time software synthesis with multiple operational modes. 98-103
  
• Júlio C. B. de Mattos, Emilena Specht, Bruno Neves, Luigi Carro:
  Making object oriented efficient for embedded system applications. 104-109
  

Digital circuits design

• Richard E. Billo, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte, Eduardo Wanderley Netto:
  Design of a decompressor engine on a SPARC processor. 110-114
  
• Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes:
  Current mask generation: a transistor level security against DPA attacks. 115-120
  
• Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt:
  Single event transients in combinatorial circuits. 121-126
  

RF CMOS design

• Leonardo Barboni, Rafaella Fiorelli:
  Design and power optimization of CMOS RF blocks operating in the moderate inversion region. 127-132
  
• C. P. Moreira, Eric Kerherve, Pierre Jarry, Didier Belot:
  Dual-standard BiCMOS LNA for DCS1800/W-CDMA applications. 133-137
  
• C. P. Moreira, A. A. Shirakawa, Eric Kerherve, Jean-Marie Pham, Pierre Jarry, Didier Belot, P. Ancey:
  Design of a fully-integrated BiCMOS/FBAR reconfigurable RF receiver front-end. 138-143
  
• Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije:
  A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer. 144-148
  
• Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Caviglia:
  Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing. 149-153
  

Low power digital circuits design

• Frank Sill, Frank Grassert, Dirk Timmermann:
  Total leakage power optimization with improved mixed gates. 154-159
  
• Shugang Wei:
  Number conversions between RNS and mixed-radix number system based on Modulo (2^{p - 1}) signed-digit arithmetic. 160-165
  
• Mariano Aguirre, Monico Linares:
  An alternative logic approach to implement high-speed low-power full adder cells. 166-171
  
• M. Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro:
  Design of a radix-2^m hybrid array multiplier using carry save adder format. 172-177
  

Networks-on-chip

• Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes:
  Virtual channels in networks on chip: implementation and evaluation on hermes NoC. 178-183
  
• Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes:
  Traffic generation and performance evaluation for mesh-based NoCs. 184-189
  
• Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Flávio Rech Wagner, Altamiro Amadeu Susin:
  Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. 190-195
  
• José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin:
  Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. 196-201
  

A-D converters and analog design

• Conrado Rossi, Pablo Aguirre:
  Ultra-low power CMOS cells for temperature sensors. 202-206
  
• Carlos Dualibe, Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni:
  New low-voltage electrically tunable triode-MOSFET transconductor and its application to low-frequency Gm-C filtering. 207-212
  
• Alfredo Arnaud:
  An efficient chopper amplifier, using a switched Gm-C Filter technique. 213-218
  
• Jung Hyun Choi:
  Minimization of parasitic effects on the design of an accurate 2-MHz RC oscillator for low voltage and low power applications. 219-223
  

System-on-chip communication and reconfigurable systems

• Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini:
  Fault tolerance overhead in network-on-chip flow control schemes. 224-229
  
• Sujan Pandey, Manfred Glesner, Max Mühlhäuser:
  Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. 230-235
  
• Florian Dittmann, Markus Heberling:
  Placement of intermodule connections on partially reconfigurable devices. 236-241
  
• Elvio Dutra, Leandro Soares Indrusiak, Manfred Glesner:
  Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator. 242-247
  
• David Varghese, J. N. Ross:
  A continuous-time hierarchical field programmable analogue array for rapid prototyping and hierarchical approach to analogue systems design. 248-253
  

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