11. IOLTS 2005: Saint Raphael, France


Session 1: Transient Fault Modeling and Analysis

Session 2: Transient Faults' Hardening Techniques

Session 3: SEU Effects in FPGAs

Special Session 1: Robust Design Techniques for Soft Errors

Special Session 2: Simulation and Mitigation of Single Event Effects

Special Session 3: Self Calibrating Design

Special Session 4: Secure Implementations

Session 4: On-Line Testing for Secure and Asynchronous Chips

Session 5: Self Checking Strategies

Session 6: Process Variations, Leakage, and Power Supply Noise Detection and Tolerance

Session 7: Posters


Session 8: Testing Issues

Session 9: SoC Testing and Fault Tolerance

Session 10: Multiple Bit Upset Evaluation and Correction

Session 11: Timing, Yield, and Reliability Issues

Special Session 5: Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing

maintained by Schloss Dagstuhl LZI at University of Trier