Introduction

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  Welcome.
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  Organizing Committee.
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  Program Committee.
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  IEEE Computer Society TTTC: Test Technology Technical Council.

Session 1: Transient Fault Modeling and Analysis

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  Tino Heijmen: Analytical Semi-Empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits. 3-8
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  Alexandre Douin, Vincent Pouget, Dean Lewis, Pascal Fouillat, Philippe Perdu: Electrical Modeling for Laser Testing with Different Pulse Durations. 9-13
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  Piotr Gawkowski, Janusz Sosnowski, B. Radko: Analyzing the Effectiveness of Fault Hardening Procedures. 14-19

Session 2: Transient Faults' Hardening Techniques

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  José Manuel Cazeaux, Daniele Rossi, Martin Omaña, Cecilia Metra, Abhijit Chatterjee: On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. 23-28
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  Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis: On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. 29-34
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  Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra: Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. 35-40

Session 3: SEU Effects in FPGAs

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  Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes: Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. 43-48
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  Monica Alderighi, A. Candelori, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Alessandro Paccagnella, Sandro Pastore, Giacomo R. Sechi: Heavy Ion Effects on Configuration Logic of Virtex FPGAs. 49-53
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  Matteo Sonza Reorda, Luca Sterpone, Massimo Violante: Efficient Estimation of SEU Effects in SRAM-Based FPGAs. 54-59

Special Session 1: Robust Design Techniques for Soft Errors

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  Yervant Zorian, Valery A. Vardanian, K. Aleksanyan, K. Amirkhanyan: Impact of Soft Error Challenge on SoC Design. 63-68
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  T. M. Mak, Subhasish Mitra, Ming Zhang: DFT Assisted Built-In Soft Error Resilience. 69
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  Robert C. Aitken, Betina Hold: Modeling Soft-Error Susceptibility for IP Blocks. 70-73
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  Ishwar Parulkar, Robert Cypher: Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems. 74-77

Special Session 2: Simulation and Mitigation of Single Event Effects

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  Lorena Anghel, Michael Nicolaidis: Simulation and Mitigation of Single Event Effects. 81
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  Frederic Wrobel: Use of Nuclear Codes for Neutron-Induced Nuclear Reactions in Microelectronics. 82-86
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  Guillaume Hubert, Nadine Buard, Cécile Weulersse, Thierry Carrière, Marie-Catherine Palau, Jean-Marie Palau, Damien Lambert, Jacques Baggio, Frederic Wrobel, Frédéric Saigné, Rémi Gaillard: A Review of DASIE Code Family: Contribution to SEU/MBU Understanding. 87-94
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  Michael Nicolaidis: Design for Mitigation of Single Event Effects. 95-96

Special Session 3: Self Calibrating Design

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  T. M. Mak: Does It Mean Less Testing for Self Calibrating Design?. 99
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  Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy: Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. 100-105
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  Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt: On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST). 106-111

Special Session 4: Secure Implementations

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  Régis Leveugle: Introduction to the Special Session on Secure Implementations. 115
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  Antoine Lemarechal: Introduction to Fault Attacks on Smartcard. 116
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  Laurent Sourgen: Security Constraints in Integrated Circuits. 117
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  Lejla Batina, Nele Mentens, Ingrid Verbauwhede: Side-Channel Issues for Designing Secure Hardware Implementations. 118-121
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  Alain Merle, Jessy Clédière: Security Testing for Hardware Products: The Security Evaluations Practice. 122-125

Session 4: On-Line Testing for Secure and Asynchronous Chips

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  Yannick Monnet, Marc Renaudin, Régis Leveugle: Hardening Techniques against Transient Faults for Asynchronous Circuits. 129-134
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  Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Deepali Koppad: On-Line Testing of Globally Asynchronous Circuits. 135-140
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  Vitalij Ocheretnij, G. Kouznetsov, Ramesh Karri, Michael Gössel: On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations. 141-146

Session 5: Self Checking Strategies

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  Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou: Fast, Parallel Two-Rail Code Checker with Enhanced Testability. 149-156
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  Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev: Power-Balanced Self Checking Circuits for Cryptographic Chips. 157-162
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  Martin Omaña, O. Losco, Cecilia Metra, Andrea Pagni: On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. 163-168

Session 6: Process Variations, Leakage, and Power Supply Noise Detection and Tolerance

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  Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy: Process Variation Tolerant Online Current Monitor for Robust Systems. 171-176
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  Bartomeu Alorda, Sebastiàn A. Bota, Jaume Segura: A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. 177-182
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  André K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra: Coding Techniques for Low Switching Noise in Fault Tolerant Busses. 183-189

Session 7: Posters

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  Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache: Modeling of Transients Caused by a Laser Attack on Smart Cards. 193-194
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  Riccardo Mariani, Gabriele Boschi: Scrubbing and Partitioning for Protection of Memory Systems. 195-196
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  Andrzej Krasniewski: A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory. 197-198
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  Amandeep Singh, Debashish Bose: A Software Based Online Memory Test for Highly Available Systems. 199-200
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  Gian-Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano: Design of a Self Checking Reed Solomon Encoder. 201-202
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  Kentaroh Katoh, Abderrahim Doumar, Hideo Ito: Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. 203-204
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  Amir Rajabzadeh: A 32-Bit COTS-Based Fault-Tolerant Embedded System. 205-206
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  Fabian Vargas, D. L. Cavalcante, Edmundo Gatti, Dárcio Prestes, D. Lupi: On the Proposition of an EMI-Based Fault Injection Approach. 207-208

Panel

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  Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert: On-Line Testing for Secure Implementations: Design and Validation. 211

Session 8: Testing Issues

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  Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis: Accumulator-Based Weighted Pattern Generation. 215-220
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  Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir: A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage. 221-226
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  George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis: Test Generation Methodology for High-Speed Floating Point Adders. 227-232

Session 9: SoC Testing and Fault Tolerance

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  Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda: Integrating BIST Techniques for On-Line SoC Testing. 235-240
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  René Kothe, Christian Galke, Heinrich Theodor Vierhaus: A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. 241-246
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  Michele Portolan, Régis Leveugle: On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. 247-252

Session 10: Multiple Bit Upset Evaluation and Correction

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  Erik Schüler, Luigi Carro: Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators. 255-259
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  Régis Leveugle: A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. 260-265
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  Balkaran S. Gill, Michael Nicolaidis, Christos A. Papachristou: Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM. 266-271

Session 11: Timing, Yield, and Reliability Issues

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  Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. 275-280
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  Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira: Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test. 281-286
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  Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy: A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. 287-292

Special Session 5: Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing

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  Yves Crouzet, Jacques Henri Collet, Jean Arlat: Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing. 295-298
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  Christian Boléat, Gerard Colas: Overview of Soft Errors Issues in Aerospace Systems. 299-302
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  Raoul Velazco, R. Ecoffet, F. Faure: How to Characterize the Problem of SEU in Processors and Representative Errors Observed on Flight. 303-308
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  Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert: Evaluation of SET and SEU Effects at Multiple Abstraction Levels. 309-312
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  Nicolas Renaud: How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family. 313-314
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  Michel Pignol: How to Cope with SEU/SET at System Level?. 315-318
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  Andre L. R. Pouponnot: Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future. 319-323

last updated on Thu May 23 03:33:12 2013 by the dblp team
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