11. FPGA 2003: Monterey, CA, USA

Novel architectures

• Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton:
  Architectures and algorithms for synthesizable embedded programmable logic cores. 3-11
  
• David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose:
  The Stratix^TM routing and logic architecture. 12-20
  
• Andrea Lodi, Mario Toma, Fabio Campi:
  A pipelined configurable gate array for embedded processors. 21-30
  

Placement

• Michael G. Wrighton, André DeHon:
  Hardware-assisted simulated annealing with application for fast FPGA placement. 33-42
  
• Pak K. Chan, Martine D. F. Schlag:
  Parallel placement for field-programmable gate arrays. 43-50
  
• Wai-Kei Mak:
  I/O placement for FPGAs with multiple I/O standards. 51-57
  

Routing

• Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun:
  Wire type assignment for FPGA routing. 61-67
  
• Akshay Sharma, Carl Ebeling, Scott Hauck:
  PipeRoute: a pipelining-aware router for FPGAs. 68-77
  
• Randy Huang, John Wawrzynek, André DeHon:
  Stochastic, spatial routing for hypergraphs, trees, and meshes. 78-87
  

Prototyping, verification, and test

• Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Robert W. Brodersen:
  Implementation of BEE: a real-time large-scale hardware emulation engine. 91-99
  
• Joydeep Ray, James C. Hoe:
  High-level modeling and FPGA prototyping of microprocessors. 100-107
  
• Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz Reis:
  Reducing pin and area overhead in fault-tolerant FPGA-based designs. 108-117
  

Device-level design

• Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald:
  A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology. 145-153
  
• Raphael Rubin, André DeHon:
  Design of FPGA interconnect for multilevel metalization. 154-163
  
• Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose:
  Automatic transistor and physical design of FPGA tiles from an architectural specification. 164-172
  

Architecture analysis and automation

• Fei Li, Deming Chen, Lei He, Jason Cong:
  Architecture evaluation for power-efficient FPGAs. 175-184
  
• Nicholas Weaver, Yury Markovsky, Yatish Patel, John Wawrzynek:
  Post-placement C-slow retiming for the xilinx virtex FPGA. 185-194
  
• Katarzyna Leijten-Nowak, Jef L. van Meerbergen:
  An FPGA architecture with enhanced datapath functionality. 195-204
  

Applications

• Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä:
  A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. 207-215
  
• François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat:
  A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. 216-224
  
• Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang:
  Energy-efficient signal processing using FPGAs. 225-234
  

Poster session

• Prithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson:
  Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. 237
  
• Sanat Kamal Bahl, Jim Plusquellic:
  FPGA implementation of a fast Hadamard transformer for WCDMA. 237
  
• M. A. Hannan Bin Azhar, Keith R. Dimond:
  FPGA-based design of an evolutionary controller for collision-free robot navigation. 237
  
• Khaled Benkrid, S. Sukhsawas, Danny Crookes, S. Belkacemi:
  A single-FPGA implementation of image connected component labelling. 238
  
• Khaled Benkrid, S. Belkacemi, Danny Crookes:
  A logic based approach to hardware abstraction. 238
  
• Abdsamad Benkrid, Danny Crookes, Khaled Benkrid:
  Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA. 238
  
• Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe:
  An estimation and exploration methodology from system-level specifications: application to FPGAs. 239
  
• Stephan Bingemer, Peter Zipf, Manfred Glesner:
  A granularity-based classification model for systems-on-a-chip. 239
  
• Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes:
  Design of a fingerprint system using a hardware/software environment. 240
  
• Elaheh Bozorgzadeh, Majid Sarrafzadeh:
  Customized regular channel design in FPGAs. 240
  
• Katherine Compton, Scott Hauck:
  Track placement: orchestrating routing structures to maximize routability. 241
  
• Joan Carletta, Robert J. Veillette, Frederick W. Krach, Zhengwei Fang:
  Implementation of digital fixed-point approximations to continuous-time IIR filters. 241
  
• Hossam A. ElGindy, George Ferizis:
  On hiding latency in reconfigurable systems: the case of merge-sort for an FPGA-based system. 242
  
• Mehrdad Eslami Dehkordi, Stephen Dean Brown:
  Recursive circuit clustering for minimum delay and area. 242
  
• Pedro C. Diniz, Joonseok Park:
  Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures. 242
  
• Binlin Guo, Jiarong Tong:
  A SC-based novel configurable analog cell. 243
  
• Yongquan Fan, Zeljko Zilic:
  Testing for bit error rate in FPGA communication interfaces. 243
  
• Soheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh:
  On computation and resource management in an FPGA-based computation environment. 243
  
• Alex K. Jones, Prithviraj Banerjee:
  An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. 244
  
• Adrian J. Hilton, Gemma Townson, Jon G. Hall:
  FPGAs in critical hardware/software systems. 244
  
• Frank Honoré, Benton H. Calhoun, Anantha Chandrakasan:
  Power-aware architectures and circuits for FPGA-based signal processing. 244
  
• Fatih Kocan:
  Reconfigurable randomized K-way graph partitioning. 245
  
• Paul D. Kundarewich, Jonathan Rose:
  Synthetic circuit generation using clustering and iteration. 245
  
• Parag K. Lala, B. Kiran Kumar:
  An FPGA architecture with built-in error correction capability. 245
  
• Zdenek Pohl, Rudolf Matousek, Jiri Kadlec, Milan Tichý, Miroslav Lícko:
  Lattice adaptive filter implementation for FPGA. 246
  
• Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni:
  Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. 246
  
• Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou:
  A physical retiming algorithm for field programmable gate arrays. 247
  
• Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat:
  Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES. 247
  
• Mehdi Baradaran Tahoori:
  A high resolution diagnosis technique for open and short defects in FPGA interconnects. 248
  
• Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald, Russell P. Kraft, Bryan S. Goda:
  A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. 248
  
• Mehdi Baradaran Tahoori:
  Application-dependent testing of FPGAs for bridging faults. 248
  

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