Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDESSCIRC 2004: Leuven, Belgium
- Michiel Steyaert, C. L. Claeys:
33rd European Solid-State Circuits Conference, ESSCIRC 2004, Leuven, Belgium, September 21-23, 2004. IEEE 2004 - Carel J. van der Poel, Francesco Pessolano, Raf Roovers, Frans Widdershoven, G. de Walle, Emile H. L. Aarts, Phillip Christie:
On ambient intelligence, needful things and process technologies. 3-10 - Takayasu Sakurai:
Low power digital circuit design. 11-18 - Roland Thewes, Christian Paulus, Meinrad Schienle, Franz Hofmann, Alexander Frey, Ralf Brederlow
, Petra Schindler-Bauer, Marcin K. Augustyniak, Melanie Atzesberger, Birgit Holzapfl, Martin Jenkner, Björn Eversmann, Gottfried Beer, Michaela Fritz, Thomas Haneder, Hans-Christian Hanke:
Integrated circuits for the biology-to-silicon interface [biotechnology]. 19-28 - Qiuting Huang:
Low voltage and low power aspects of data converter design. 29-35 - Herman Casier, Peter Moens, Koen Appeltans:
Technology considerations for automotive. 37-41 - John F. M. Gerrits, John R. Farserotu, John R. Long:
UWB considerations for "my personal global adaptive network" (MAGNET) systems. 45-56 - Maarten Vertregt, Peter C. S. Scholtens:
Assessment of the merits of CMOS technology scaling for analog circuit design. 57-63 - Gene A. Frantz:
DSP: a technology, a product, a revolution. 65-68 - Vincent J. Arkesteijn, Eric A. M. Klumperink, Bram Nauta:
A wideband high-linearity RF receiver front-end in CMOS. 71-74 - Egidio Ragonese, Alessandro Italia, Luca La Paglia, Giuseppe Palmisano:
Silicon bipolar up and down-converters for 5-GHz WLAN applications. 75-78 - Minkyung Lee, Ickjin Kwon, Kwyro Lee:
An integrated low power CMOS baseband analog design for direct conversion receiver. 79-82 - Wolfgang Winkler, Johannes Borngräber, Hans Gustat, Falk Korndörfer:
60 GHz transceiver circuits in SiGe:C BiCMOS technology. 83-86 - Jongmoon Kim, Sanghyun Cho, Jinho Ko:
L1/L2 dual-band CMOS GPS receiver. 87-90 - Jere A. M. Järvinen, Jouni Kaukovuori, Jussi Ryynänen, Jarkko Jussila, Kalle Kivekäs, Kari A. I. Halonen:
2.4-GHz receiver for sensor applications. 91-94 - David Chamla, Andreas Kaiser, Andreia Cathelin, Didier Belot:
A multi-mode continuously-tunable lowpass filter for zero-IF mobile applications. 95-98 - Shinichi Hori, Tadashi Maeda, Noriaki Matsuno, Hikaru Hida:
Low-power widely tunable Gm-C filter with an adaptive DC-blocking, triode-biased MOSFET transconductor. 99-102 - Bo Shi, Weiyun Shan:
A Gm-C baseband filter with automatic frequency tuning for a direct conversion IEEE802.11a wireless LAN receiver. 103-106 - Paolo Bruschi, Giuseppe Barillaro, Francesco Pieri, Massimo Piotto:
Temperature stabilised tunable Gm-C filter for very low frequencies. 107-110 - Faramarz Bahmani, Edgar Sánchez-Sinencio:
A highly linear pseudo-differential transconductance [CMOS OTA]. 111-114 - Belén Calvo, Santiago Celma, Maria Teresa Sanz:
A high-linear 160-MHz CMOS PGA [programmable gain amplifier]. 115-118 - Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Performance degradation of an LC-tank VCO by impact of digital switching noise. 119-122 - Hyman Shanan, Michael Peter Kennedy:
A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators. 123-126 - Jan Craninckx, Vincent Gravot, Stéphane Donnay:
A harmonic quadrature LO generator using a 90° delay-locked loop [zero-IF transceiver applications]. 127-130 - Wolfgang Winkler, Johannes Borngräber, Bernd Heinemann:
LC-oscillators above 100 GHz in silicon-based technology. 131-134 - Ken Yamamoto, Minoru Fujishima:
55GHz CMOS frequency divider with 3.2GHz locking range. 135-138 - Kostas Manetakis, Darryl Jessie, Chiewcharn Narathong:
A wideband CMOS VCO for zero-IF GSM-CDMA single-chip transceiver. 139-142 - Xiaohong Peng, Willy Sansen:
Transconductance with capacitances feedback compensation for multistage amplifiers. 143-146 - Shouri Chatterjee, Yannis P. Tsividis, Peter R. Kinget:
A 0.5-V bulk-input fully differential operational transconductance amplifier. 147-150 - Dirk Killat, Oliver Salzmann, Andreas Baumgaertner:
A 14-V high speed driver in 5-V-only 0.35-μm standard CMOS. 151-154 - Vittorio Colonna, Marzia Annovazzi, Gianluigi Boarin, Gabriele Gandolfi, Fabrizio Stefani, Andrea Baschirotto:
A 0.22mm2 7.25mW per-channel audio stereo-DAC with 97dB-DR and 39dB SNRout. 155-158 - Johan Sommarek, Jouko Vankka, Jaakko Ketola, Jonne Lindeberg, Kari Halonen:
A digital modulator with bandpass delta-sigma modulator. 159-162 - Dario Giotta, Peter Pessl, Martin Clara, Wolfgang Klatzer, Richard Gaggl:
Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13μm CMOS. 163-166 - Tao Chen, Peter Geens, Geert Van der Plas, Wim Dehaene, Georges G. E. Gielen:
A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL. 167-170 - Mindaugas Draidiiulis, Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson:
A power cut-off technique for gate leakage suppression [CMOS logic circuits]. 171-174 - Klaus von Arnim, Eduardo Borinski, Peter Seegebrecht, Horst Fiedler, Ralf Brederlow, Roland Thewes, Jörg Berthold, Christian Pacha:
Efficiency of body biasing in 90 nm CMOS for low power digital circuits. 175-178 - Kris Tiri, Ingrid Verbauwhede:
Charge recycling sense amplifier based logic: securing low power security ICs against DPA [differential power analysis]. 179-182 - Markus Schimper, Lukas Dörrer, Ettore Riccio, Georgi Panov:
A 3mW continuous-time ΣΔ-modulator for EDGE/GSM with high adjacent channel tolerance. 183-186 - Michiel A. P. Pertijs, Johan H. Huijsing:
A sigma-delta modulator with bitstream-controlled dynamic element matching. 187-190 - Prasad Ammisetti, Amiya Chokhawala, Karl Thompson, John Melanson:
A 120dB 300mW stereo audio A/D converter with 110dB THD+N. 191-194 - Jan van Sinderen, Marc Notten, Eduard Stikvoort, Francois Seneschal:
A 48-860 MHz TV splitter amplifier exhibiting an IIP2 and IIP3 of 94dBmV and 73dBmV. 195-198 - Nico Boom, Wim Rens, Jan Crols:
A 5.0mW 0dBm FSK transmitter for 315/433 MHz ISM applications in 0.25 μm CMOS. 199-202 - Antonino Scuderi, Francesco Carrara, Guiseppe Palmisano:
A 5.2-GHz silicon bipolar power amplifier for IEEE 802.11a and HIPERLAN2 wireless LANs. 203-206 - Ferdinando Bedeschi, Roberto Bez, Chiara Boffino, Edoardo Bonizzoni, Egidio Cassiodoro Buda, Giulio Casagrande, Lucio Costa, Marco Ferraro, Roberto Gastaldi, Osama Khouri, Federica Ottogalli, Fabio Pellizzer, Agostino Pirovano, Claudio Resta, Guido Torelli, Marina Tosi:
4-Mb MOSFET-selected phase-change memory experimental chip. 207-210 - Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Anirudh Devgan:
Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. 211-214 - Ingvar Carlson, Stefan Anderson, Sreedhar Natarajan, Atila Alvandpour:
A high density, low leakage, 5T SRAM for embedded caches. 215-218 - Binjie Cheng, Scott Roy, Asen Asenov:
The impact of random doping effects on CMOS SRAM cell. 219-222 - Robert Swoboda, Johannes Knorr, Horst Zimmermann:
A 2.4GHz-bandwidth OEIC with voltage-up-converter [optical receiver]. 223-226 - Olivier Charlon, William Redman-White:
Ultra high-compliance CMOS current mirrors for low voltage charge pumps and references. 227-230 - Antonio Lopez-Martin, Sushmita Baswa, Jaime Ramírez-Angulo, Ramón G. Carvajal:
Power-efficient super class AB OTAs. 231-234 - Sotir Ouzounov, Engel Roza, Hans Hegt, Gerard van der Weide, Arthur H. M. van Roermund:
CMOS V-I converter with 75dB SFDR and 360μW power consumption. 235-238 - Franz Schlögl, Horst Zimmermann:
1.5 GHz OPAMP in 120nm digital CMOS. 239-242 - Wolfgang Horn, Peter Singerl:
Thermally optimized demagnetization of inductive loads [power IC load switching]. 243-246 - Terje N. Andersen, Atle Briskemyr, Frode Telstø, Johnny Bjørnsen, Thomas E. Bonnerud, Bjørnar Hernes, Øystein Moldsvor:
A 97mW 110MS/s 12b pipeline ADC implemented in 0.18μm digital CMOS. 247-250 - David Muthers, Reinhard Tielert:
A 0.11mm2 low-power A/D-converter cell for 10b 10MS/s operation. 251-254 - Pierangelo Confalonieri, Marco Zamprogno, Francesca Girardi, Germano Nicollini, Angelo Nagari:
A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges. 255-258 - Bo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio:
A configurable time-interleaved pipeline ADC for multi-standard wireless receivers. 259-262 - Wei-Zen Chen, Ying-Lien Cheng:
A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end. 263-266 - Johannes Sturm, Martin Leifhelm, Harald Schatzmayr, Stefan Groiss, Horst Zimmermann:
Optical receiver IC for CD/DVD/blue-laser application. 267-270 - Marco Giardina, A. Stek, G. W. de Jong, Jos R. M. Bergervoet:
Design of low noise CMOS OEIC for blu-ray disc optical storage systems. 271-274 - Carolien Hermans, Paul Leroux, Michiel Steyaert:
Two high-speed optical front-ends with integrated photodiodes in standard 0.18 μm CMOS. 275-278 - Lianming Li, Ting Huang, Jun Feng, Zhigong Wang, Mingzhen Xiong:
5 Gbps 0.35-μm CMOS driver for laser diode or optical modulator. 279-282 - Yong-Hun Oh, Quan Le, Sang-Gug Lee, Nguyen Duy Bien Yen, Ho-Yong Kang, Tae-Whan Yoo:
Burst-mode transmitter for 1.25Gb/s Ethernet PON applications [passive optical networks]. 283-286 - Michael Gordon, Sorin P. Voinigescu:
An inductor-based 52-GHz 0.18 μm SiGe HBT cascode LNA with 22 dB gain. 287-290 - Dimitri Linten, Steven Thijs, Mahadeva Iyer Natarajan, Piet Wambacq, Wutthinan Jeamsaksiri, Javier Ramos, Abdelkarim Mercha, Snezana Jenei, Stéphane Donnay, Stefaan Decoutere:
A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS. 291-294 - Paul Leroux, Michiel Steyaert:
A 5 GHz CMOS low-noise amplifier with inductive ESD protection exceeding 3 kV HBM. 295-298 - Urs Frey, Markus Graf, Stefano Taschini, Kay-Uwe Kirstein, Christoph Hagleitner, Andreas Hierlemann, Henry Baltes:
A digital CMOS micro-hotplate array for analysis of environmentally relevant gases. 299-302 - Andreas Burg, Markus Wenk, Martin Zellweger, Marc Simon Wegmueller, Norbert Felber, Wolfgang Fichtner:
VLSI implementation of the sphere decoding algorithm. 303-306 - Norbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Towards an AES crypto-chip resistant to differential power analysis. 307-310 - Makoto Ogawa, Tadashi Shibata:
A delay-encoding-logic array processor for dynamic programming matching. 311-314 - Kamran Farzan, David A. Johns:
A power-efficient 4-PAM signaling scheme with convolutional encoder in space for chip-to-chip communication. 315-318 - Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho:
Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver IC. 319-322 - Atul Katoch, Manish Garg, Evert Seevinck, Harry J. M. Veendrick:
Adaptive threshold scheme to operate long on-chip buses at the limit of signal integrity. 323-326 - Xinzhong Duo, Tommi Torikka, Li-Rong Zheng, Mohammed Ismail, Hannu Tenhunen:
On-chip versus off-chip passives in multi-band radio design. 327-330 - Manuel Delgado-Restituto, A. J. Acosta, Ángel Rodríguez-Vázquez:
A mixed-signal integrated circuit for FM-DCSK modulation. 331-334 - Roc Berenguer, Erik Hernández, N. Rodríguez, Iosu Cendoya, Armando Muñoz, Héctor Solar:
Design of a highly integrated tuner suitable for analog and digital TV systems. 335-338 - Christoph Sandner, Martin Clara, Andreas Santner, Thomas Hartig, Franz Kuttner:
A 6bit, 1.2GSps low-power flash-ADC in 0.13μm digital CMOS. 339-342 - Simon M. Louwsma, Ed J. M. van Tuijl, Maarten Vertregt, Peter C. S. Scholtens, Bram Nauta:
A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. 343-346 - Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hirovuki Okada:
4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]. 347-350 - Bryan Atwood, Tomoyuki Ishii, Takao Watanabe, Toshiyuki Mine, Norifumi Kameshiro, Toshiaki Sano, Kazuo Yano:
A cavity channel SESO embedded memory with low standby-power techniques. 351-354 - Kiyoshi Ishii, Hideyuki Nosaka, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Takatorno Enoki, Tsugumichi Shibata:
High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]. 355-358 - Hugo Veenstra:
1-58 Gb/s PRBS generator with <1.1 ps RMS jitter in InP technology. 359-362 - (Withdrawn) Notice of Violation of IEEE Publication PrinciplesA 10GHz SiGe OC192 frequency synthesizer using a passive feed-forward loop filter and a half rate oscillator. 363-366
- N. Pavlovic, J. Gosselin, K. Mistry, D. Leenaerts:
A 10 GHz frequency synthesiser for 802.11a in 0.18 μm CMOS [transceiver applications]. 367-370 - Nicola Da Dalt, Edwin Thaller, Peter Gregorius, Lajos Gazsi:
A low jitter triple-band digital LC PLL in 130nm CMOS. 371-374 - Tsung-Te Liu, Chorng-Kuang Wang:
A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator. 375-378 - Chun-Seok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih:
Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. 379-382 - Sung-Eun Kim, Seong-Jun Song, Jin Kyung Kim, Sunyoung Kim, Jae-Youl Lee, Hoi-Jun Yoo:
A small ripple regulated charge pump with automatic pumping control schemes. 383-386 - Wim Van de Maele, F. Stevens, A. Huot-Marchand, B. Sekerkiran:
A mixed-signal chip with HV-protected pins in 0.35-μm-based HV-technology. 387-390 - Goichi Ono, Masayuki Miyazaki, Hidetoshi Tanaka, Nono Ohkubo, Takayuki Kawahara:
Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors]. 391-394 - Amir M. Fahim:
A low-power clock generator for system-on-a-chip (SoC) processors. 395-398 - Jan F. J. Wouters, Jan Sevenhans, Stefaan Van Hoogenbemt, Thierry Fernandez, Jeff Biggs, Carl Das, Steven Dupont:
A novel active feedback flyback [inductive load driver]. 399-402 - Hiroyuki Hara, Mikio Sakurai, Mitsutoshi Miyasaka, Simon W. B. Tam, Satoshi Inoue, Tatsuya Shimoda:
Low temperature polycrystalline silicon TFT fingerprint sensor with integrated comparator circuit. 403-406 - Ger de Graaf, Lukas Mol, Luís A. Rocha, Edmond Cretu, Reinoud F. Wolffenbuttel:
Quadrature oscillator with pre-distorted waveforms for application in MEMS-based mechanical spectrum analyser. 407-410 - Werner Brockherde, Arndt Bußmann, Christian Nitta, Bedrich J. Hosticka, Reiner K. Wertheimer:
High-sensitivity, high-dynamic range 768 × 576 pixel CMOS image sensor. 411-414 - Felix Lustenberger, M. Lehmann, L. Cavalier, Nicolas Blanc, W. Heppner, J. Ernst, S. Gick, H. Bloss:
A colour 3200fps high-speed CMOS imager for endoscopy in bio-medical applications. 415-418 - David Stoppa, Luigi Viarani, Andrea Simoni, Lorenzo Gonzo, Mattia Malfatti, Gianmaria Pedretti:
A 16×16-pixel range-finding CMOS image sensor. 419-422 - Ahmed Nader Mohieldin, Edgar Sánchez-Sinencio:
A dual-mode low-pass filter for 802.11b/Bluetooth receiver. 423-426 - Jani Pehkonen, Juha Kostamovaara:
An integrated laser radar receiver with resonance-based timing discrimination. 427-430 - Ickjin Kwon, Kwyro Lee:
A low power highly linear 2.4 GHz CMOS receiver front-end using current amplifier. 431-434 - Christian Grewing, Martin Friedrich, Giuseppe Li Puma, Christoph Sandner, Stefan van Waasen, Andreas Wiesbauer, Kay Winterberg:
Fully integrated ultra wide band CMOS low noise amplifier. 435-438 - Chun-Pang Wu, Hen-Wai Tsao:
A 100 MHz timing generator for impulse radio applications. 439-442 - Mario Motz, Dieter Draxelmayr, Tobias Werth, Bernhard Forster:
A chopped Hall sensor with programmable "true power-on" function. 443-446 - Luc Vander Voorde, K. Appeltans, Javier Alonso:
An EMC-robust high voltage system-on-chip. 447-450 - Ger de Graaf, Reinoud F. Wolffenbuttel:
Circuit for readout and linearisation of sensor bridges. 451-454 - Jean-Denis Techer, Serge Bernard, Yves Bertrand, Guy Cathébras, David Guiraud:
New implantable stimulator for the FES of paralyzed muscles. 455-458 - Eric Compagne, Stephane Maulet, Sebastien Genevey:
An analog front-end for remote sensor applications with high input common-mode rejection including a 16bit ΣΔ ADC in 0.35μm 3.3V CMOS process. 459-462 - Kay-Uwe Kirstein, Jan Sedivý, Tomi Salo, Christoph Hagleitner, Tobias Vancura, Henry Baltes:
A CMOS-based tactile sensor for continuous blood pressure monitoring. 463-466 - Tobias Gemmeke, Tobias G. Noll:
A physically oriented model to quantify the dynamic noise margin [on-chip noise]. 467-470 - Antonino Conte, Gianbattista Lo Giudice, Gaetano Palumbo, Alfredo Signorello:
A 1.35-V sense amplifier for non volatile memories based on current mode approach. 471-474 - Peter Caputa, Mark A. Anders, Christer Svensson, Ram K. Krishnamurthy, Shekhar Borkar:
A low-swing single-ended L1 cache bus technique for sub-90nm technologies. 475-477 - Antonio Giuseppe Maria Strollo, Nicola Petra, Davide De Caro, Ettore Napoli:
An area-efficient high-speed Reed-Solomon decoder in 0.25 μm CMOS. 479-482 - Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
A dual mode channel decoder for 3GPP2 mobile wireless communications. 483-486 - Tomas Geurts, Wim Rens, Jan Crols, Shoichiro Kashiwakura, Yuichi Segawa:
A 2.5 Gbps - 3.125 Gbps multi-core serial-link transceiver in 0.13 μm CMOS. 487-490 - Paul Muller, Yusuf Leblebici, Matthew K. Emsley, M. Selim Ünlü:
A 4-channel 2.5Gb/s/channel 66dBΩ inductorless transimpedance amplifier [optical receiver applications]. 491-494
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-30 21:02 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
