Luca Fanucci (Ed.):
11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008.
IEEE 2008, ISBN 978-0-7695-3277-6 Prospective Aspects of Networks-on-Chip
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NEWCOM++:
Flexible Radio Digital Design
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Fault Tolerance in Digital System Design - I
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System-Level Energy Optimization of Embedded Software
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Carlo Brandolese :
Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software.
115-123
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MPSOC and Interconnects
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Video and Image Processing
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conf/dsd/TulabandhulaPC08 export record as
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conf/dsd/ColenbranderDKVM08
Fault Tolerance in Digital System Design - II
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Andrzej Krasniewski :
Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs.
250-255
Power Issues
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Sudip Roy ,
Ajit Pal :
Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?
282-289
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conf/dsd/ZamanzadehMNPS08 export record as
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Design, Modeling and Verification of Cache and Cache-based Systems
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FPGA and Reconfigurable Architectures - I
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conf/dsd/CecchiniSBMBFM08 export record as
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Applications of Digital Systems
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conf/dsd/BaldrighiCVCGF08 export record as
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conf/dsd/BaldrighiMCVCB08 export record as
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conf/dsd/LamprehtSVZMBP08
Synthesis
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conf/dsd/Risco-MartinAHL08 export record as
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conf/dsd/Garcia-RepettoMRB08 export record as
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Planning and Optimization of Sensor Network Systems - I
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Hardware Checking
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A. Neslin Ismailoglu ,
Murat Askar :
SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation.
566-571
FPGA and Reconfigurable Architectures - II
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Design Methodologies
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Planning and Optimization of Sensor Network Systems - II
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conf/dsd/Morales-RamosVPB08 export record as
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Dependability and Testing of Digital Systems - I
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Jiri Jenícek :
Efficient Test Pattern Compression Method Using Hard Fault Preferring.
703-708
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Digital Signal Processing - I
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System Synthesis
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Wireless Systems
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Dependability and Testing of Digital Systems - II
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conf/dsd/DamavandpeymaM08 export record as
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Josef Strnadel :
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path.
865-872
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Digital Signal Processing - II
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Parallel Architectures
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