CODES+ISSS 2006: Seoul, Korea

HW/SW design exploration for multimedia applications

Low power scheduling and estimation techniques

System-level performance issues

Transaction-level modeling and exploration

Architecture and modeling for network-on-chip

Embedded security and reliability

Advanced Techniques for high-level synthesis and physical design

Design optimization for network-on-chip

Application-specific code optimization


Programming models for multiprocessor systems: from supercomputing programming to multiprocessors on a chip

Simulation, optimization, and acceleration

System-level design of MPSoC

System-level optimization

Architecture exploration

Industry solutions to emerging embedded systems

Synthesis techniques for accelerators

Communication synthesis and analysis for MPSoC

maintained by Schloss Dagstuhl LZI at University of Trier