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Publication search results
found 90 matches
- 2013
- Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
TSV capacitance aware 3-D floorplanning. 3DIC 2013: 1-6 - Masahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi:
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 3DIC 2013: 1-5 - Erfan Azarkhish, Igor Loi, Luca Benini:
A high-performance multiported L2 memory IP for scalable three-dimensional integration. 3DIC 2013: 1-8 - Yann Beilliard, Perceval Coudrain, Léa Di Cioccio, Stéphane Moreau, Loic Sanchez, Brigitte Montmayeul, Thomas Signamarcheix, Rafael Estevez, Guillaume Parry:
Chip to wafer copper direct bonding electrical characterization and thermal cycling. 3DIC 2013: 1-7 - Tomasz Bieniek, Grzegorz Janczyk, Rafal Dobrowolski, Dariusz Szmigiel, Magdalena Ekwinska, Piotr Grabiec, Pawel Janus, Jerzy Zajac:
Dedicated MEMS-based test structure for 3D SiP interconnects reliability investigation. 3DIC 2013: 1-6 - Melanie Brocard, Cédric Bermond, Thierry Lacrevaz, Alexis Farcy, Patrick Le Maitre, P. Scheer, Patrick Leduc, Séverine Cheramy, Bernard Fléchet:
RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits. 3DIC 2013: 1-8 - Jui-Chin Chen, John H. Lau, Tzu-Chien Hsu, Chien-Chou Chen, Pei-Jer Tzeng, Po-Chih Chang, Chun-Hsien Chien, Yiu-Hsiang Chang, Shang-Chun Chen, Yu-Chen Hsin, Sue-Chen Liao, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao:
Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer. 3DIC 2013: 1-5 - Jason Chew, Uday Mahajan, Rajeev Bajaj, Iad Mirshad, Robert Newcomb:
Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination. 3DIC 2013: 1-6 - Jason Chew, Uday Mahajan, Rajeev Bajaj, Iad Mirshad, Robert Newcomb:
Characterization and optimization of a TSV CMP reveal process using a novel wafer inspection technique for detecting sub-monolayer surface contamination. 3DIC 2013: 1-6 - Chun-Hsien Chien, Hsun Yu, Ching-Kuan Lee, Yu-Min Lin, Ren-Shin Cheng, Chau-Jie Zhan, Peng-Shu Chen, Chang-Chih Liu, Chao-Kai Hsu, Hsiang-Hung Chang, Huan-Chun Fu, Yuan-Chang Lee, Wen-Wei Shen, Cheng-Ta Ko, Wei-Chung Lo, Yung Jean Lu:
Performance and process characteristic of glass interposer with through-glass-via(TGV). 3DIC 2013: 1-7 - Jonghyun Cho, Youngwoo Kim, Joungho Kim, Venky Sundaram, Rao R. Tummala:
Analysis of glass interposer PDN and proposal of PDN resonance suppression methods. 3DIC 2013: 1-5 - Jonghyun Cho, Youngwoo Kim, Joungho Kim, Venky Sundaram, Rao R. Tummala:
Analysis of glass interposer PDN and proposal of PDN resonance suppression methods. 3DIC 2013: 1-5 - Gerald Cibrario, David Henry, Chantal Chantre, Robert Cuchet, Robert Berthelot, Karim Azizi-Mourier, Marjorie Gary, Fabien Gays:
A 3D Process Design Kit generator based on customizable 3D layout design environment. 3DIC 2013: 1-5 - Yann Civale, Herman Meynen, Ranjith S. E. John, Peng-Fei Fu, Craig R. Yeakle, Sheng Wang, Stefan Krausse, Thomas Rapps, Stefan Lutter:
Cost-effective temporary bonding and debonding material solution towards high-volume manufacturing 2.5D/3D through-silicon via integrated circuits. 3DIC 2013: 1-5 - Thorbjorn Ebefors, Jessica Fredlund, Daniel Perttu, Raymond van Dijk, Lorenzo Cifola, Mikko Kaunisto, Pekka Rantakari, Tauno Vaha-Heikkila:
The development and evaluation of RF TSV for 3D IPD applications. 3DIC 2013: 1-8 - Ryusuke Egawa, Masayuki Sato, Jubee Tada, Hiroaki Kobayashi:
Vertically integrated processor and memory module design for vector supercomputers. 3DIC 2013: 1-6 - Paul D. Franzon, Avi Bar-Cohen:
Thermal requirements in future 3D processors. 3DIC 2013: 1-6 - Ricardo I. Fuentes:
Wafer thinning for 3D integration. 3DIC 2013: 1-5 - Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Mitsumasa Koyanagi:
Development of via-last 3D integration technologies using a new temporary adhesive system. 3DIC 2013: 1-4 - Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Ho-Young Son, M.-S. Suh, K.-Y. Byun, N.-S. Kim, Kang Wook Lee, Mitsumasa Koyanagi:
3D memory chip stacking by multi-layer self-assembly technology. 3DIC 2013: 1-4 - Kaushik Ghosh, C. C. Yap, Beng Kang Tay, Chuan Seng Tan:
Integration of CNT in TSV (≤5 μm) for 3D IC application and its process challenges. 3DIC 2013: 1-4 - Dipanjan Gope, S. Chatterjee, D. de Araujo, Swagato Chakraborty, James Pingenot, Raul Camposano:
Device physics aware 3D electromagnetic simulation of Through-Silicon-Vias in system modeling. 3DIC 2013: 1-5 - Neela Gopi, Jeffrey Draper:
Techniques for assigning inter-tier signals to bondpoints in a face-to-face bonded 3DIC. 3DIC 2013: 1-6 - Hiroyuki Hashimoto, Takafumi Fukushima, Kang Wook Lee, Mitsumasa Koyanagi, Tetsu Tanaka:
Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. 3DIC 2013: 1-5 - Andy Heinig:
Layout dependent synthesis for manufacturing costs optimized 3D integrated systems. 3DIC 2013: 1-6 - Nahid M. Hossain, MunEm Hossain, Abdul Hamid Bin Yousuf, Masud H. Chowdhury:
Thermal aware Graphene based Through Silicon Via design for 3D IC. 3DIC 2013: 1-4 - Yan-Pin Huang, Ruoh-Ning Tzeng, Yu-San Chien, Ming-Shaw Shy, Teu-Hua Lin, Kuo-Hua Chen, Ching-Te Chuang, Wei Hwang, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen:
Low temperature (<180 °C) bonding for 3D integration. 3DIC 2013: 1-5 - Akihiro Ikeda, L. J. Qiu, K. Nakahara, Tanemasa Asano:
Surface passivation of Cu cone bump by self-assembled-monolayer for room temperature Cu-Cu bonding. 3DIC 2013: 1-4 - Sylvain Joblot, Alexis Farcy, Nicolas Hotellier, Amadine Jouve, François de Crecy, Arnaud Garnier, M. Argoud, C. Ferrandon, J.-P. Colonna, R. Franiatte, C. Laviron, Séverine Cheramy:
Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration. 3DIC 2013: 1-7 - Daniel H. Jung, Jonghyun Cho, Heegon Kim, Jonghoon J. Kim, Hongseok Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi:
Fault isolation of short defect in through silicon via (TSV) based 3D-IC. 3DIC 2013: 1-4
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