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Publication search results
found 19 matches
- 1997
- Luca Benini, Patrick Vuillod, Alessandro Bogliolo, Giovanni De Micheli:
Clock Skew Optimization for Peak Current Reduction. J. VLSI Signal Process. 16(2-3): 117-130 (1997) - Keith M. Carrig, Albert M. Chu, Frank D. Ferraiolo, John G. Petrovick, P. Andrew Scott, Richard J. Weiss:
A Clock Methodology for High-Performance Microprocessors. J. VLSI Signal Process. 16(2-3): 217-224 (1997) - Eby G. Friedman:
High Performance Clock Distribution Networks. J. VLSI Signal Process. 16(2-3): 113-116 (1997) - Kris Gaj, Eby G. Friedman, Marc J. Feldman:
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits. J. VLSI Signal Process. 16(2-3): 247-276 (1997) - Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela:
Clock Distribution Methodology for PowerPCTM Microprocessors. J. VLSI Signal Process. 16(2-3): 181-189 (1997) - David J. Hathaway, Rafik R. Habra, Erich C. Schanzenbach, Sara J. Rothman:
Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology. J. VLSI Signal Process. 16(2-3): 191-198 (1997) - Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon
, Ralph K. Cavin III:
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews. J. VLSI Signal Process. 16(2-3): 131-147 (1997) - Kazuhito Ito, Keshab K. Parhi:
A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis. J. VLSI Signal Process. 16(1): 57-72 (1997) - Masahiro Iwadare, Hideto Takano, Yoshitaka Shibuya, Hideki Sakamoto, Takeshi Kuwajima, Osamu Kitabatake, Naoko Kobayashi:
A Single-Chip MPEG/Audio Decoder LSI Based on a Compact Decoding Algorithm. J. VLSI Signal Process. 16(1): 25-30 (1997) - Andrew B. Kahng, Chung-Wen Albert Tsao:
Practical Bounded-Skew Clock Routing. J. VLSI Signal Process. 16(2-3): 199-215 (1997) - Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch:
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. J. VLSI Signal Process. 16(1): 31-40 (1997) - Won Namgoong, Teresa H. Meng:
A Low-Power Encoder For Pyramid Vector Quantization of Subband Coefficients. J. VLSI Signal Process. 16(1): 9-23 (1997) - José Luis Neves, Eby G. Friedman:
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. J. VLSI Signal Process. 16(2-3): 149-161 (1997) - Keshab K. Parhi, Takao Nishitani, Hironori Yamauchi:
Guest Editors' Introduction. J. VLSI Signal Process. 16(1): 5-7 (1997) - Stuart K. Tewksbury, Lawrence A. Hornak:
Optical Clock Distribution in Electronic Systems. J. VLSI Signal Process. 16(2-3): 225-246 (1997) - David W. Trainor, Roger F. Woods, John V. McCanny:
Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". J. VLSI Signal Process. 16(1): 41-55 (1997) - Joe G. Xi, Wayne Wei-Ming Dai:
Useful-Skew Clock Routing with Gate Sizing for Low Power Design. J. VLSI Signal Process. 16(2-3): 163-179 (1997) - Anissa Zergaïnoh, Pierre Duhamel, Jean Pierre Vidal:
Efficient Implementation Methodology of Fast FIR Filtering Algorithms on DSP. J. VLSI Signal Process. 16(1): 81-103 (1997) - Vojin Zivojnovic, Steven W. K. Tjiang, Heinrich Meyr:
Compiled Simulation of Programmable DSP Architectures. J. VLSI Signal Process. 16(1): 73-80 (1997)
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