"Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for ..."

José Luis Neves, Eby G. Friedman (1997)

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DOI: 10.1023/A:1007986907060

access: closed

type: Journal Article

metadata version: 2020-05-20

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José Luis Neves, Eby G. Friedman:
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. J. VLSI Signal Process. 16(2-3): 149-161 (1997)

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