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Publication search results
found 25 matches
- 1997
- Mahmoud Al-Qutayri, Peter R. Shepherd:
Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal Circuits. VLSI Design 5(3): 223-240 (1997) - Víctor H. Champac, Joan Figueras:
Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects. VLSI Design 5(3): 273-284 (1997) - Mandalagiri S. Chandrasekhar, Robert H. McCharles, David E. Wallace:
Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits. VLSI Design 5(2): 125-140 (1997) - Nikil D. Dutt, Pradip K. Jha:
RT Component Sets for High-Level Design Applications. VLSI Design 5(2): 155-165 (1997) - Ian G. Harris, Alex Orailoglu:
Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction. VLSI Design 5(2): 167-182 (1997) - Suntae Hwang, Rochit Rajsuman:
VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing. VLSI Design 5(3): 299-311 (1997) - Eugeni Isern, Joan Figueras:
IDDQ Detectable Bridges in Combinational CMOS Circuits. VLSI Design 5(3): 241-252 (1997) - Fadi J. Kurdahi:
Linking Behavioral, Structural, and Physical Models of Hardware. VLSI Design 5(2): i-ii (1997) - Rafic Z. Makki:
Advancements in Power Supply Current Testing. VLSI Design 5(3): i-ii (1997) - Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong:
Operational and Test Performance in the Presence of Built-in Current Sensors. VLSI Design 5(3): 285-298 (1997) - Massoud Pedram, Narasimha B. Bhat, Ernest S. Kuh:
Combining Technology Mapping With Layout. VLSI Design 5(2): 111-124 (1997) - Abdulnour Y. Toukmaji, Ronald Helms, Rafic Z. Makki, Wadie Mikhail, Patrick Toole:
IDDQ Testing Experiments for Various CMOS Logic Design Structures. VLSI Design 5(3): 253-271 (1997) - Fur-Shing Tsai, Yu-Chin Hsu:
Layout Modeling and Design Space Exploration in Pss1 System. VLSI Design 5(2): 211-221 (1997) - Akhilesh Tyagi:
Statistical Module Level Area and Delay Estimation. VLSI Design 5(2): 141-153 (1997) - Jen-Pin Weng, Alice C. Parker:
Taking Thermal Considerations Into Account During High-Level Synthesis. VLSI Design 5(2): 183-193 (1997) - Allen C.-H. Wu:
Datapath Optimization Using Layout Information: An Empirical Study. VLSI Design 5(2): 195-209 (1997) - 1996
- Dinesh Bhatia, V. Shankar:
Greedy Segmented Channel Router. VLSI Design 5(1): 11-21 (1996) - Kuo-En Chang, Sei-Wang Chen:
An Efficient and Fast Algorithm for Routing Over the Cells. VLSI Design 5(1): 1-10 (1996) - Donald T. Comer:
Zener Zap Anti-Fuse Trim in VLSI Circuits. VLSI Design 5(1): 89-100 (1996) - Gudni Gudmundsson, Simeon C. Ntafos:
A Greedy Algorithm for Over-The-Cell Channel Routing. VLSI Design 5(1): 23-36 (1996) - Bhanu Kapoor, V. S. S. Nair:
Improving Path Sensitizability of Combinational Circuits. VLSI Design 5(1): 49-57 (1996) - Murray W. Pearson, Paul J. Lyons, Mark D. Apperley:
High-Level Graphical Abstraction in Digital Design. VLSI Design 5(1): 101-110 (1996) - C. P. Ravikumar, Vikram Saxena:
TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis. VLSI Design 5(1): 77-87 (1996) - Youssef Saab:
A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing Performance. VLSI Design 5(1): 37-48 (1996) - Jiabi Zhu, Mostafa I. H. Abd-El-Barr, Carl McCrosky:
A New Theory for Testability-Preserving Optimization of Combinational Circuits. VLSI Design 5(1): 59-75 (1996)
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