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@article{DBLP:journals/vlsi/Al-QutayriS97,
  author       = {Mahmoud Al{-}Qutayri and
                  Peter R. Shepherd},
  title        = {Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal
                  Circuits},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {3},
  pages        = {223--240},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/47423},
  doi          = {10.1155/1997/47423},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/Al-QutayriS97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ChampacF97,
  author       = {V{\'{\i}}ctor H. Champac and
                  Joan Figueras},
  title        = {Current Testing of {CMOS} Combinational Circuits with Single Floating
                  Gate Defects},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {3},
  pages        = {273--284},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/97381},
  doi          = {10.1155/1997/97381},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/ChampacF97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ChandrasekharMW97,
  author       = {Mandalagiri S. Chandrasekhar and
                  Robert H. McCharles and
                  David E. Wallace},
  title        = {Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis
                  of Area and Speed-Efficient Circuits},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {2},
  pages        = {125--140},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/30941},
  doi          = {10.1155/1997/30941},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/ChandrasekharMW97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/DuttJ97,
  author       = {Nikil D. Dutt and
                  Pradip K. Jha},
  title        = {{RT} Component Sets for High-Level Design Applications},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {2},
  pages        = {155--165},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/35614},
  doi          = {10.1155/1997/35614},
  timestamp    = {Tue, 06 Dec 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/DuttJ97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/HarrisO97,
  author       = {Ian G. Harris and
                  Alex Orailoglu},
  title        = {Module Selection in Microarchitectural Synthesis for Multiple Critical
                  Constraint Satisfaction},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {2},
  pages        = {167--182},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/81902},
  doi          = {10.1155/1997/81902},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/HarrisO97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/HwangR97,
  author       = {Suntae Hwang and
                  Rochit Rajsuman},
  title        = {{VLSI} Testing for High Reliability: Mixing {IDDQ} Testing With Logic
                  Testing},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {3},
  pages        = {299--311},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/59329},
  doi          = {10.1155/1997/59329},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/HwangR97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/IsernF97,
  author       = {Eugeni Isern and
                  Joan Figueras},
  title        = {I\({}_{\mbox{DDQ}}\) Detectable Bridges in Combinational {CMOS} Circuits},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {3},
  pages        = {241--252},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/93809},
  doi          = {10.1155/1997/93809},
  timestamp    = {Wed, 20 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/IsernF97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Kurdahi97,
  author       = {Fadi J. Kurdahi},
  title        = {Linking Behavioral, Structural, and Physical Models of Hardware},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {2},
  pages        = {i--ii},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/27279},
  doi          = {10.1155/1997/27279},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/Kurdahi97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Makki97,
  author       = {Rafic Z. Makki},
  title        = {Advancements in Power Supply Current Testing},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {3},
  pages        = {i--ii},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/90247},
  doi          = {10.1155/1997/90247},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/Makki97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MenonMJT97,
  author       = {Sankaran M. Menon and
                  Yashwant K. Malaiya and
                  Anura P. Jayasumana and
                  Carol Q. Tong},
  title        = {Operational and Test Performance in the Presence of Built-in Current
                  Sensors},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {3},
  pages        = {285--298},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/54757},
  doi          = {10.1155/1997/54757},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/MenonMJT97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/PedramBK97,
  author       = {Massoud Pedram and
                  Narasimha B. Bhat and
                  Ernest S. Kuh},
  title        = {Combining Technology Mapping With Layout},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {2},
  pages        = {111--124},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/73654},
  doi          = {10.1155/1997/73654},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/PedramBK97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ToukmajiHMMT97,
  author       = {Abdulnour Y. Toukmaji and
                  Ronald Helms and
                  Rafic Z. Makki and
                  Wadie Mikhail and
                  Patrick Toole},
  title        = {I\({}_{\mbox{DDQ}}\) Testing Experiments for Various {CMOS} Logic
                  Design Structures},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {3},
  pages        = {253--271},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/51094},
  doi          = {10.1155/1997/51094},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/ToukmajiHMMT97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/TsaiH97,
  author       = {Fur{-}Shing Tsai and
                  Yu{-}Chin Hsu},
  title        = {Layout Modeling and Design Space Exploration in Pss1 System},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {2},
  pages        = {211--221},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/42849},
  doi          = {10.1155/1997/42849},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/TsaiH97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Tyagi97,
  author       = {Akhilesh Tyagi},
  title        = {Statistical Module Level Area and Delay Estimation},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {2},
  pages        = {141--153},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/78238},
  doi          = {10.1155/1997/78238},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/Tyagi97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/WengP97,
  author       = {Jen{-}Pin Weng and
                  Alice C. Parker},
  title        = {Taking Thermal Considerations Into Account During High-Level Synthesis},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {2},
  pages        = {183--193},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/39186},
  doi          = {10.1155/1997/39186},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/WengP97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Wu97,
  author       = {Allen C.{-}H. Wu},
  title        = {Datapath Optimization Using Layout Information: An Empirical Study},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {2},
  pages        = {195--209},
  year         = {1997},
  url          = {https://doi.org/10.1155/1997/85473},
  doi          = {10.1155/1997/85473},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/Wu97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/BhatiaS96,
  author       = {Dinesh Bhatia and
                  V. Shankar},
  title        = {Greedy Segmented Channel Router},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {1},
  pages        = {11--21},
  year         = {1996},
  url          = {https://doi.org/10.1155/1996/53512},
  doi          = {10.1155/1996/53512},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/BhatiaS96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ChangC96,
  author       = {Kuo{-}En Chang and
                  Sei{-}Wang Chen},
  title        = {An Efficient and Fast Algorithm for Routing Over the Cells},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {1},
  pages        = {1--10},
  year         = {1996},
  url          = {https://doi.org/10.1155/1996/96136},
  doi          = {10.1155/1996/96136},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/ChangC96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Comer96,
  author       = {Donald T. Comer},
  title        = {Zener Zap Anti-Fuse Trim in {VLSI} Circuits},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {1},
  pages        = {89--100},
  year         = {1996},
  url          = {https://doi.org/10.1155/1996/23706},
  doi          = {10.1155/1996/23706},
  timestamp    = {Mon, 28 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/Comer96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/GudmundssonN96,
  author       = {Gudni Gudmundsson and
                  Simeon C. Ntafos},
  title        = {A Greedy Algorithm for Over-The-Cell Channel Routing},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {1},
  pages        = {23--36},
  year         = {1996},
  url          = {https://doi.org/10.1155/1996/10797},
  doi          = {10.1155/1996/10797},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/GudmundssonN96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/KapoorN96,
  author       = {Bhanu Kapoor and
                  V. S. S. Nair},
  title        = {Improving Path Sensitizability of Combinational Circuits},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {1},
  pages        = {49--57},
  year         = {1996},
  url          = {https://doi.org/10.1155/1996/61747},
  doi          = {10.1155/1996/61747},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/KapoorN96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/PearsonLA96,
  author       = {Murray W. Pearson and
                  Paul J. Lyons and
                  Mark D. Apperley},
  title        = {High-Level Graphical Abstraction in Digital Design},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {1},
  pages        = {101--110},
  year         = {1996},
  url          = {https://doi.org/10.1155/1996/69892},
  doi          = {10.1155/1996/69892},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/PearsonLA96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RavikumarS96,
  author       = {C. P. Ravikumar and
                  Vikram Saxena},
  title        = {{TOGAPS:} {A} Testability Oriented Genetic Algorithm For Pipeline
                  Synthesis},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {1},
  pages        = {77--87},
  year         = {1996},
  url          = {https://doi.org/10.1155/1996/65320},
  doi          = {10.1155/1996/65320},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/RavikumarS96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Saab96,
  author       = {Youssef Saab},
  title        = {A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing
                  Performance},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {1},
  pages        = {37--48},
  year         = {1996},
  url          = {https://doi.org/10.1155/1996/58084},
  doi          = {10.1155/1996/58084},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/Saab96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ZhuAM96,
  author       = {Jiabi Zhu and
                  Mostafa I. H. Abd{-}El{-}Barr and
                  Carl McCrosky},
  title        = {A New Theory for Testability-Preserving Optimization of Combinational
                  Circuits},
  journal      = {{VLSI} Design},
  volume       = {5},
  number       = {1},
  pages        = {59--75},
  year         = {1996},
  url          = {https://doi.org/10.1155/1996/19043},
  doi          = {10.1155/1996/19043},
  timestamp    = {Sat, 05 Nov 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/ZhuAM96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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