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Publication search results
found 167 matches
- 2014
- Hao Zheng, Yingying Zhang:
Local State Space Analysis Leads to Better Partial Order Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 839-852 (2014) - Mukesh Agrawal, Michael Richter, Krishnendu Chakrabarty:
Test-Delivery Optimization in Manycore SOCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1067-1080 (2014) - Hussam Amrouch, Thomas Ebi, Jörg Henkel:
RESI: Register-Embedded Self-Immunity for Reliability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 677-690 (2014) - Matthew Amy, Dmitri Maslov, Michele Mosca:
Polynomial-Time T-Depth Optimization of Clifford+T Circuits Via Matroid Partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1476-1489 (2014) - Bardia Bandali, Emad Gad, Miodrag Bolic:
Accelerated Harmonic-Balance Analysis Using a Graphical Processing Unit Platform. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(7): 1017-1030 (2014) - Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal:
Verification of Code Motion Techniques Using Value Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1180-1193 (2014) - Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal:
Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 2015-2019 (2014) - Cinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone:
ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1342-1355 (2014) - Hans Georg Brachtendorf, Robert C. Melville, Peter Feldmann, Siegmar Lampe, Rainer Laur:
Homotopy Method for Finding the Steady States of Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 867-878 (2014) - Andrea Calimera, Mirko Loghi, Enrico Macii, Massimo Poncino:
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 251-264 (2014) - Yu Cao, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, Michael Fritze:
Cross-Layer Modeling and Simulation of Circuit Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 8-23 (2014) - En-Jui Chang, Hsien-Kai Hsin, Shu-Yen Lin, An-Yeu Wu:
Path-Congestion-Aware Adaptive Routing With a Contention Prediction Scheme for Network-on-Chip Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 113-126 (2014) - Da-Wei Chang, Ing-Chao Lin, Yu-Shiang Chien, Ching-Lun Lin, Alvin W. Y. Su, Chung-Ping Young:
CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1806-1817 (2014) - Chip-Hong Chang, Li Zhang:
A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 76-89 (2014) - Yu-Guang Chen, Hui Geng, Kuan-Yu Lai, Yiyu Shi, Shih-Chieh Chang:
Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 507-518 (2014) - Weiwei Chen, Xu Han, Che-Wei Chang, Guantao Liu, Rainer Dömer:
Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1859-1872 (2014) - Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li:
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 24-35 (2014) - Da Cheng, Sandeep K. Gupta:
Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(10): 1545-1558 (2014) - Jaeyong Chung, Yonghyun Kim, Joon-Sung Yang:
3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 2005-2009 (2014) - Christopher Condrat, Priyank Kalla, Steve Blair:
Crossing-Aware Channel Routing for Integrated Optics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 814-825 (2014) - Jordi Cortadella, Jordi Petit, Sergio Gómez, Francesc Moll:
A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 409-422 (2014) - Pallab Dasgupta, Mandayam K. Srivas, Rajdeep Mukherjee:
Formal Hardware/Software Co-Verification of Embedded Power Controllers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 2025-2029 (2014) - Sergej Deutsch, Krishnendu Chakrabarty:
Contactless Pre-Bond TSV Test and Diagnosis Using Ring Oscillators and Multiple Voltage Levels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 774-785 (2014) - Georgios D. Dimou, Peter A. Beerel, Andrew Lines:
Performance-Driven Clustering of Asynchronous Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 197-209 (2014) - Hassan Eldib, Chao Wang:
An SMT Based Method for Optimizing Arithmetic Computations in Embedded Software Code. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1611-1622 (2014) - Shao-Yun Fang, Yao-Wen Chang, Wei-Yu Chen:
A Novel Layout Decomposition Algorithm for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 397-408 (2014) - Alexander Finder, André Sülflow, Görschwin Fey:
Latency Analysis for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 643-647 (2014) - Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis:
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 546-557 (2014) - Mohammad H. Foroozannejad, Matin Hashemi, Alireza Mahini, Bevan M. Baas, Soheil Ghiasi:
Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 752-762 (2014) - Sahar Foroutan, Abbas Sheibanyrad, Frédéric Pétrot:
Assignment of Vertical-Links to Routers in Vertically-Partially-Connected 3-D-NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1208-1218 (2014)
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