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Publication search results
found 188 matches
- 2010
- Hao Zheng:
Compositional Reachability Analysis for Efficient Modular Verification of Asynchronous Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 329-340 (2010) - Qiang Ma, Evangeline F. Y. Young:
Multivoltage Floorplan Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 607-617 (2010) - Vincent Acary, Olivier Bonnefon, Bernard Brogliato:
Time-Stepping Numerical Simulation of Switched Circuits Within the Nonsmooth Dynamical Systems Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1042-1055 (2010) - Bijan Alizadeh, Masahiro Fujita:
Modular Datapath Optimization and Verification Based on Modular-HED. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1422-1435 (2010) - Bijan Alizadeh, Mohammad Mirzaei, Masahiro Fujita:
Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 737-748 (2010) - Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak:
On Reducing Scan Shift Activity at RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1110-1120 (2010) - Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 788-801 (2010) - Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet:
High-Level Synthesis for Designing Multimode Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1736-1749 (2010) - Mohammad Arjomand, Hamid Sarbazi-Azad:
Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer Allocation Schemes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1558-1571 (2010) - Mauro Ballicchia, Simone Orcioni:
Design and Modeling of Optimum Quality Spiral Inductors With Regularization and Debye Approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1669-1681 (2010) - Alp Arslan Bayrakci, Alper Demir, Serdar Tasiran:
Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1328-1341 (2010) - Giovanni Beltrame, Luca Fossati, Donatella Sciuto:
Decision-Theoretic Design Space Exploration of Multiprocessor Platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1083-1095 (2010) - Amir Beygi, Anestis Dounavis:
Sensitivity Analysis of Lossy Multiconductor Transmission Lines Based on the Passive Method of Characteristics Macromodel. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1290-1294 (2010) - Roderick Bloem, Patrick Schaumont:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1457-1458 (2010) - Peter Böhm:
Incremental and Verified Modeling of the PCI Express Protocol. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1495-1508 (2010) - Bradley N. Bond, Zohaib Mahmood, Yan Li, Ranko Sredojevic, Alexandre Megretski, Vladimir Stojanovic, Yehuda Avniel, Luca Daniel:
Compact Modeling of Nonlinear Analog Circuits Using System Identification via Semidefinite Programming and Incremental Stability Certification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1149-1162 (2010) - Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani:
FSSA: Fast Steady-State Algorithm for the Analysis of Mixed Analog/Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 528-537 (2010) - Xavier Briand, Bertrand Jeannet:
Combining Control and Data Abstraction in the Verification of Hybrid Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1481-1494 (2010) - Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1096-1109 (2010) - Svetozar S. Broussev, Nikolay T. Tchamov:
Time-Varying Root-Locus of Large-Signal LC Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 830-834 (2010) - Gianpiero Cabodi, Luz Amanda Garcia, Marco Murciano, Sergio Nocco, Stefano Quer:
Partitioning Interpolant-Based Verification for Effective Unbounded Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 382-395 (2010) - Stephen Cauley, Venkataramanan Balakrishnan, Cheng-Kok Koh:
A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 636-641 (2010) - Krishnendu Chakrabarty, Richard B. Fair, Jun Zeng:
Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1001-1017 (2010) - Ashutosh Chakraborty, Sean X. Shi, David Z. Pan:
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1533-1545 (2010) - Chip-Hong Chang, Mathias Faust:
On "A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 844-848 (2010) - Yen-Jung Chang, Yu-Ting Lee, Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang:
NTHU-Route 2.0: A Robust Global Router for Modern Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1931-1944 (2010) - Gang Chen:
Formalization of a Parameterized Parallel Adder Within the Coq Theorem Prover. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 149-153 (2010) - Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng:
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1709-1722 (2010) - Po-Lin Chen, Yu-Chieh Huang, Tsin-Yuan Chang:
Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1837-1842 (2010) - Fu-Wei Chen, Yi-Yu Liu:
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 2046-2050 (2010)
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