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Publication search results
found 59 matches
- 2000
- Magdy S. Abadir:
Guest Editorial. J. Electron. Test. 16(1-2): 9-10 (2000) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(1-2): 5 (2000) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(3): 163 (2000) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(4): 315 (2000) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(5): 403-404 (2000) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 16(6): 571 (2000) - Hussain Al-Asaad, John P. Hayes:
Logic Design Validation via Simulation and Automatic Test Pattern Generation. J. Electron. Test. 16(6): 575-589 (2000) - Bechir Ayari, Prab Varma:
Test Cycle Count Reduction in a Parallel Scan BIST Environment. J. Electron. Test. 16(5): 409-418 (2000) - Alfredo Benso, Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Yervant Zorian:
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. J. Electron. Test. 16(3): 179-184 (2000) - Surendra Bommu, Kiran B. Doreswamy, Srimat T. Chakradhar:
A Practical Vector Restoration Technique for Large Sequential Circuits. J. Electron. Test. 16(5): 521-539 (2000) - Pradip Bose:
Testing for Function and Performance: Towards an Integrated Processor Validation Methodology. J. Electron. Test. 16(1-2): 29-48 (2000) - Anna Maria Brosa, Joan Figueras:
On Maximizing the Coverage of Catastrophic and Parametric Faults. J. Electron. Test. 16(3): 251-258 (2000) - Kanad Chakraborty, Pinaki Mazumder:
New March Tests for Multiport RAM Devices. J. Electron. Test. 16(4): 389-395 (2000) - Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick:
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. J. Electron. Test. 16(1-2): 13-27 (2000) - Chen-Huan Chiang, Sandeep K. Gupta:
BIST TPG for Combinational Cluster Interconnect Testing at Board Level. J. Electron. Test. 16(5): 427-442 (2000) - Serge N. Demidenko:
Guest Editorial. J. Electron. Test. 16(5): 407-408 (2000) - John Marty Emmert, Dinesh K. Bhatia:
A Fault Tolerant Technique for FPGAs. J. Electron. Test. 16(6): 591-606 (2000) - Michele Favalli, Cecilia Metra:
Bridging Faults in Pipelined Circuits. J. Electron. Test. 16(6): 617-629 (2000) - Stefan Gerstendörfer, Hans-Joachim Wunderlich:
Minimized Power Consumption for Scan-Based BIST. J. Electron. Test. 16(3): 203-212 (2000) - Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi:
False-Path Removal Using Delay Fault Simulation. J. Electron. Test. 16(5): 463-476 (2000) - Emil Gizdarski:
Detection of Delay Faults in Memory Address Decoders. J. Electron. Test. 16(4): 381-387 (2000) - Said Hamdioui, Ad J. van de Goor:
Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy. J. Electron. Test. 16(5): 487-498 (2000) - Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electron. Test. 16(5): 443-451 (2000) - Michael S. Hsiao, Srimat T. Chakradhar:
Test Set Compaction Using Relaxed Subsequence Removal. J. Electron. Test. 16(4): 319-327 (2000) - Michael S. Hsiao, Srimat T. Chakradhar:
Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits. J. Electron. Test. 16(4): 329-338 (2000) - André Ivanov, Vikram Devdas:
Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study. J. Electron. Test. 16(6): 631-634 (2000) - Abdelhakim Khouas, Anne Derieux:
Fault Simulation for Analog Circuits Under Parameter Variations. J. Electron. Test. 16(3): 269-278 (2000) - Gundolf Kiefer, Hans-Joachim Wunderlich:
Deterministic BIST with Partial Scan. J. Electron. Test. 16(3): 169-177 (2000) - Christian Landrault:
Guest Editorial. J. Electron. Test. 16(3): 167 (2000) - Xiaowei Li, Paul Y. S. Cheung, Hideo Fujiwara:
LFSR-Based Deterministic TPG for Two-Pattern Testing. J. Electron. Test. 16(5): 419-426 (2000)
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