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Publication search results
found 50 matches
- 2015
- Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin:
Virtual reconfigurable scan-chains on FPGAs for optimized board test. LATS 2015: 1-6 - Florence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre:
A digital technique for the evaluation of SSB phase noise of analog/RF signals. LATS 2015: 1-6 - Paolo Bernardi, Lyl M. Ciganda Brasca, Matteo Sonza Reorda, Said Hamdioui:
SW-based transparent in-field memory testing. LATS 2015: 1-6 - Rigoberto Bracamontes-Salazar, Esdras Juárez-Hernández, Federico Lobato-Lopez, Esteban Martinez Guerrero:
CMOS amplifier with self-correction offset for SerDes applications. LATS 2015: 1-4 - J. L. Bueno-Ruiz, C. A. Arriaga-Arriaga, R. Huerta-Barrera, G. V. Cruz-Dominguez, C. H. Pimentel-Romero, Jesús M. Muñoz-Pacheco, Luz del Carmen Gómez-Pavón, Olga Guadalupe Félix-Beltrán, Arnulfo Luis-Ramos:
Fault conditions of a simple chaotic circuit under capacitor nonlinear effects. LATS 2015: 1-5 - Riccardo Cantoro, Marco Gaudesi, Ernesto Sánchez, Pasquale Davide Schiavone, Giovanni Squillero:
An evolutionary approach for test program compaction. LATS 2015: 1-6 - Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal:
Message from the LATS2015 Chairs. LATS 2015: 1 - Thiago Copetti, G. Cardoso Medeiros, Letícia Maria Bolzani Poehls, Fabian Vargas:
NBTI-aware design of integrated circuits: a hardware-based approach. LATS 2015: 1-6 - Mafalda Cortez, Said Hamdioui, Ryoichi Ishihara:
Design dependent SRAM PUF robustness analysis. LATS 2015: 1-6 - Karine Coulié-Castellani, Wenceslas Rahajandraibe, Hassen Aziza, Jean-Michel Portal, Gilles Micolau:
Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment. LATS 2015: 1-5 - Davide Ferraretto, Graziano Pravadelli:
Efficient fault injection in QEMU. LATS 2015: 1-6 - Ronaldo Rodrigues Ferreira, Ernesto Sánchez, Jean da Rolt, Gabriel L. Nazar, Álvaro F. Moreira, Luigi Carro, Matteo Sonza Reorda:
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture. LATS 2015: 1-6 - Luis Gerardo de la Fraga, Esteban Tlelo-Cuautle:
Optimizing operational amplifiers by metaheuristics and considering tolerance analysis. LATS 2015: 1-4 - Alexandro Giron-Allende, Victor Avendaño, Esteban Martinez Guerrero:
A controllable setup and propagation delay flip-flop design. LATS 2015: 1-5 - André B. M. Gomes, Fredy A. M. Alves, Ricardo S. Ferreira, José Augusto Miranda Nacif:
Vericonn: a tool to generate efficient interconnection networks for post-silicon debug. LATS 2015: 1-6 - Iuri A. C. Gomes, Mayler G. A. Martins, André Inácio Reis, Fernanda Lima Kastensmidt:
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR. LATS 2015: 1-6 - Andres F. Gomez, Víctor H. Champac:
Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability. LATS 2015: 1-6 - Ivick Guerra-Gómez, Trent McConaghy, Esteban Tlelo-Cuautle:
Study of regression methodologies on analog circuit design. LATS 2015: 1-6 - Jailene Hernandez, Johan Castrillon, Manuel Jiménez, Angel De La Torre, Pedro Escalona, Rogelio Palomera:
A virtual instrument design for low-cost charge-pumping characterization of integrated MOSFETs. LATS 2015: 1-4 - Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang:
Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS. LATS 2015: 1-6 - Alexandra Kourfali, Dirk Stroobandt:
Test set generation almost for free using a run-time FPGA reconfiguration technique. LATS 2015: 1-6 - Jaak Kousaar, Raimund Ubar, Igor Aleksejev:
Complex delay fault reasoning with sequential 7-valued algebra. LATS 2015: 1-6 - Yu-Wei Lee, Nur A. Touba:
Improving logic obfuscation via logic cone analysis. LATS 2015: 1-6 - Carlos Leong, Jorge Semião, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Fault-tolerance in FPGA focusing power reduction or performance enhancement. LATS 2015: 1-6 - Baohu Li, Bei Zhang, Vishwani D. Agrawal:
Adopting multi-valued logic for reduced pin-count testing. LATS 2015: 1-6 - Jesus Lopez-Arredondo, Esteban Tlelo-Cuautle, Rodolfo Trejo-Guerra:
Optimizing an LDO voltage regulator by evolutionary algorithms considering tolerances of the circuit elements. LATS 2015: 1-5 - Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra:
FPGA redundancy recovery based on partial bitstreams for multiple partitions. LATS 2015: 1-4 - João Guilherme Mourão Melo, Frank Sill Torres:
Noise analysis of integrated bulk current sensors for detection of radiation induced soft errors. LATS 2015: 1-6 - Takanori Moriyasu, Satoshi Ohtake:
A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults. LATS 2015: 1-6 - Sebastian Müller, Tobias Koal, Stefan Scharoba, Heinrich Theodor Vierhaus, Mario Schölzel:
A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems. LATS 2015: 1-6
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