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Publication search results
found 80 matches
- 2002
- Jason Helge Anderson, Farid N. Najm:
Power-aware technology mapping for LUT-based FPGAs. FPT 2002: 211-218 - Paul Beckett:
A fine-grained reconfigurable logic array based on double gate transistors. FPT 2002: 260-267 - Samir Belkacemi, Khaled Benkrid, Danny Crookes:
HIDE: a logic based hardware intelligent description environment. FPT 2002: 174-180 - Khaled Benkrid:
A multiplier-less FPGA core for image algebra neighbourhood operations. FPT 2002: 294-297 - Abdsamad Benkrid, Khaled Benkrid, Danny Crookes:
Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs. FPT 2002: 356-359 - Neil W. Bergmann:
Enabling technologies for reconfigurable system-on-chip. FPT 2002: 360-363 - Alex Carreira, Trevor W. Fox, Laurence E. Turner:
A method of implementing bit-serial LDI ladder filters in FPGAs using JBits. FPT 2002: 433-436 - Yu-Tsang Chang, Yu-Te Chou, Wei-Chang Tsai, Jiann-Jenn Wang, Chen-Yi Lee:
FPGA education and research activities in Taiwan. FPT 2002: 445-448 - Shih-Liang Chen, TingTing Hwang, C. L. Liu:
A technology mapping algorithm for CPLD architectures. FPT 2002: 204-210 - Paul Y. S. Cheung:
Technology research and development in Hong Kong: hype or reality. FPT 2002 - Ocean Y. H. Cheung, Philip Heng Wai Leong:
Implementation of an FPGA based accelerator for virtual private networks. FPT 2002: 34-41 - José Gabriel F. Coutinho, Wayne Luk:
Optimising and adapting high-level hardware designs. FPT 2002: 150-157 - Anwar S. Dawood, John A. Williams, Stephen J. Visser:
On-board satellite image compression using reconfigurable FPGAs. FPT 2002: 306-310 - Mehrdad Eslami Dehkordi, Stephen Dean Brown:
The effect of cluster packing and node duplication control in delay driven clustering. FPT 2002: 227-233 - Arran Derbyshire, Wayne Luk:
Compiling run-time parametrisable designs. FPT 2002: 44-51 - Andreas Fidjeland, Wayne Luk, Stephen H. Muggleton:
Scalable acceleration of inductive logic programs. FPT 2002: 252-259 - Michael J. Flynn:
Programmed solutions: the step beyond programmed logic [computer architecture]. FPT 2002: 13-16 - Ingo Fröhlich, Adrian Gabriel, Daniel Kirschner, Jörg Lehnert, Erik Lins, Markus Petri, Tiago Perez, Jim Ritman, Daniel Schäfer, Alberica Toia, Michael Traxler, Wolfgang Kuehn:
Pattern recognition in the HADES spectrometer: an application of FPGA technology in nuclear and particle physics. FPT 2002: 443-444 - Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi:
Floating-point bitwidth analysis via automatic differentiation. FPT 2002: 158-165 - D. C. Gharpure, M. S. Puranik:
FPGA implementation of MFNN for image registration. FPT 2002: 364-367 - Stefan Valentin Gheorghita, Weng-Fai Wong, Tulika Mitra, Surendranath Talla:
A co-simulation study of adaptive EPIC computing. FPT 2002: 268-275 - Derek B. Gottlieb, Jeffrey J. Cook, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter:
Clustered programmable-reconfigurable processors. FPT 2002: 134-141 - Michael Guntsch, Martin Middendorf, Bernd Scheuermann, Oliver Diessel, Hossam A. ElGindy, Hartmut Schmeck, Keith So:
Population based ant colony optimization on FPGA. FPT 2002: 125-132 - Christian Hinkelbein, Reinhard Männer:
Reconfigurable hardware control software using anonymous libraries. FPT 2002: 426-428 - John Hopf, G. Stewart Von Itzstein, David A. Kearney:
Hardware Join Java: a high level language for reconfigurable hardware development. FPT 2002: 344-347 - Yohei Hori, Masashi Sonoyama, Tsutomu Maruyama:
An FPGA-based processor for shogi mating problems. FPT 2002: 117-124 - C. H. Hsu, Trieu-Kien Truong, Ming-Haw Jing, W.-C. Wu, H. C. Wu:
The feasibility study of designing a FPGA multiplier-core on finite field. FPT 2002: 386-389 - Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen:
Strassen's matrix multiplication for customisable processors. FPT 2002: 453-456 - Sushil Chandra Jain, Anshul Kumar, Shashi Kumar:
Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards. FPT 2002: 298-301 - Ju-wook Jang, Seonil Choi, Viktor K. Prasanna:
Area and time efficient implementations of matrix multiplication on FPGAs. FPT 2002: 93-100
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retrieved on 2024-05-24 11:49 CEST from data curated by the dblp team
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