"The feasibility study of designing a FPGA multiplier-core on finite field."

C. H. Hsu et al. (2002)

> Home

Details and statistics

DOI: 10.1109/FPT.2002.1188717

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpt/HsuTJWW02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpt/HsuTJWW02
C. H. Hsu, Trieu-Kien Truong, Ming-Haw Jing, W.-C. Wu, H. C. Wu:
The feasibility study of designing a FPGA multiplier-core on finite field. FPT 2002: 386-389

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.