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Publication search results
found 146 matches
- 2000
- Thorsten Adler, Erich Barke:
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. DATE 2000: 446-450 - Lorena Anghel, Michael Nicolaidis:
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique. DATE 2000: 591-598 - Peter Bach, Michael Bosch:
Structural Testing on Real Boards. DATE 2000: 741 - Felice Balarin:
Automatic Abstraction for Worst-Case Analysis of Discrete Systems. DATE 2000: 494-501 - Massimo Baleani, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, Claudio Turchetti:
HW/SW Codesign of an Engine Management System. DATE 2000: 263-267 - Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki:
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip. DATE 2000: 141-145 - Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
A Discrete-Time Battery Model for High-Level Power Estimation. DATE 2000: 35-39 - Timothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick:
Diagnostic Testing of Embedded Memories Using BIST. DATE 2000: 305-309 - Per Bjuréus, Axel Jantsch:
MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow. DATE 2000: 161-168 - Joseph Borel, Frank Ghenassia, Jean-Jacques Bronner, Irmtraud Rugen-Herzig, Wolfgang Rosenstiel, Anton Sauer:
A Design Automation Roadmap for Europe Panel discussion. DATE 2000: 510 - Youcef Bourai, C.-J. Richard Shi:
Layout Compaction for Yield Optimization via Critical Area Minimization. DATE 2000: 122-125 - Ulrich Brenner, Jens Vygen:
Faster Optimal Single-Row Placement with Fixed Ordering. DATE 2000: 117-121 - Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn:
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation. DATE 2000: 326-332 - Joan Carletta, Christos A. Papachristou, Mehrdad Nourani:
Detecting Undetectable Controller Faults Using Power Analysis. DATE 2000: 723-728 - Luigi Carro, Márcio Eduardo Kreutz, Flávio Rech Wagner, Márcio Oyamada:
System Synthesis for Multiprocessor Embedded Applications. DATE 2000: 697-702 - Luigi Carro, Adão Antônio de Souza Jr., Marcelo Negreiros, Gabriel Parmegiani Jahn, Denis Teixeira Franco:
Non-Linear Components for Mixed Circuits Analog Front-End. DATE 2000: 544-549 - Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich:
Optimal Hardware Pattern Generation for Functional BIST. DATE 2000: 292-297 - Francky Catthoor, Nikil D. Dutt, Christoforos E. Kozyrakis:
How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? DATE 2000: 426-433 - Sunho Chang, Jong-Sun Kim, Lee-Sup Kim:
A Memory Architecture with 4-Address Configurations for Video Signal Processing. DATE 2000: 746 - Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He:
Clocktree RLC Extraction with Efficient Inductance Modeling. DATE 2000: 522-526 - Jovanka Ciric, Gin Yee, Carl Sechen:
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE 2000: 277-282 - Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo:
An Efficient Heuristic Approach to Solve the Unate Covering Problem. DATE 2000: 364-371 - Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti:
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience. DATE 2000: 385-389 - Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski:
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE 2000: 226-230 - Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli:
Virtual Fault Simulation of Distributed IP-Based Designs. DATE 2000: 99-103 - Alper Demir, Peter Feldmann:
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits. DATE 2000: 340-344 - Mohamed Dessouky, Marie-Minerve Louërat, Jacky Porte:
Layout-Oriented Synthesis of High Performance Analog Circuits. DATE 2000: 53-57 - Juan M. Díez, Juan Carlos López:
Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion. DATE 2000: 645-649 - Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty:
Transformational Placement and Synthesis. DATE 2000: 194-201 - Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio:
TOP: An Algorithm for Three-Level Optimization of PLDs. DATE 2000: 751
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