- Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally:
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC 2019: 1-4 - Jun Liu, Xianjie Wan, Mingyuan Xu, Youhua Wang, Yi Ding, Dongbing Fu:
A High Speed Clock Receiver for DAC with Cross point and Duty Cycle Adjustable Capability. ICITEE 2019: 62:1-62:4 - Gaurav Malhotra, Jalil Kamali:
Symbol spaced clock recovery for high speed links. ICSPCS 2019: 1-5 - Kyung-Soo Ha, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Jin-Hun Jang, Hyong-Ryol Hwang, Hyung-Joon Chi, Junghwan Park, Seungjun Shin, Dukha Park, Sang-Yun Kim, Sukhyun Lim, Kiwon Park, YeonKyu Choi, Young-Hwa Kim, Younghoon Son, Hyunyoon Cho, Byongwook Na, Hyo-Joo Ahn, Seungseob Lee, Seouk-Kyu Choi, Youn-Sik Park, Seok-Hun Hyun, Soobong Chang, Hyuck-Joon Kwon, Jung-Hwan Choi, Tae-Young Oh, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. ISSCC 2019: 378-380 - Jeffrey Prinzie, Szymon Kulis, Pedro Leitao, Rui Francisco, Valentijn De Smedt, Paulo Moreira, Paul Leroux:
A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS. LASCAS 2019: 63-66 - Jun Matsui, Hisakatsu Yamaguchi:
Event-Driven Model for High Speed End-to-End Simulations of Transmission System with Non-Linear Optical Elements and Cascaded Clock-and-Data Recovery Circuits. VLSI-DAT 2019: 1-4 - 2018
- Seonggeon Kim, Kang-Yoon Lee, Minjae Lee:
Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2832-2841 (2018) - Wei-Chun Lu, Ming-Yuan Yu, Pei-Chun Lin:
Clock-Torqued Rolling SLIP Model and Its Application to Variable-Speed Running in a Hexapod Robot. IEEE Trans. Robotics 34(6): 1643-1650 (2018) - Nico Angeli, Klaus Hofmann:
A Scalable Fully Synthesized Phase-to-Digital Converter for Phase and Duty-Cycle Measurement of High-Speed Clocks. ISCAS 2018: 1-5 - Min-Su Kim, Ah-Reum Kim, Yong-geol Kim, Chunghee Kim, Dong-Yeop Kim, Jong-Woo Kim, Daeseong Lee, Hyun Lee, Jungyul Pyo, Youngmin Shin, Jae Cheol Son:
Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling. ISCAS 2018: 1-5 - Matthew Schormans, Virgilio Valente, Andreas Demosthenous:
Intermittent Excitation of High-Q Resonators for Low-Power High-Speed Clock Generation. ISCAS 2018: 1-4 - Roberto Nonis, Pavan Kumar Hanumolu, Frank O'Mahony:
Session 25 overview: Clock generation for high-speed links: Wireline subcommittee. ISSCC 2018: 388-389 - 2017
- Romesh Kumar Nandwana:
Clock multiplication techniques for high-speed I/Os. University of Illinois Urbana-Champaign, USA, 2017 - Wenjian Jiang, Fengqi Yu, Qinjin Huang:
A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler. IEICE Electron. Express 14(1): 20160446 (2017) - Minglei Zhang, Xiaohua Fan:
An energy-efficient SAR ADC using a single-phase clocked dynamic comparator with energy and speed enhanced technique. IEICE Electron. Express 14(8): 20170219 (2017) - Zhibo Wang, Yongpan Liu, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Jinyang Li, Chien-Chen Lin, Wei-Hao Chen, Hsiao-Yun Chiu, Wei-En Lin, Ya-Chin King, Chrong Jung Lin, Pedram Khalili Amiri, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang:
A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed. IEEE J. Solid State Circuits 52(10): 2769-2785 (2017) - Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco:
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. IEEE Trans. Biomed. Circuits Syst. 11(5): 1133-1147 (2017) - Jia-wei Tan, Yang Guo, Jianjun Chen, Hengzhou Yuan, Xi Chen:
A state recovery design against single-event transient in high-speed phase interpolation clock and data recovery circuit. ASICON 2017: 339-342 - L. Cron, P. Laugier, Pietro Maris Ferreira, Filipe Vinci dos Santos, Philippe Bénabès:
Delay estimation and measurement circuit for a high-speed CMOS clocked comparator. ECCTD 2017: 1-4 - Eugene Koskin, Dimitri Galayko, Orla Feely, Elena Blokhina:
Semianalytical model for high speed analysis of all-digital PLL clock-generating networks. ISCAS 2017: 1-4 - Seyed Alireza Zahrai, Nicolas Le Dortz, Marvin Onabajo:
Design of clock generation circuitry for high-speed subranging time-interleaved ADCs. ISCAS 2017: 1-4 - Sarang Kazeminia, Maryam Ghafoorzadeh, Faeze Noruzpur:
An extendable global clock high-speed binary counter compatible to the FPGA CLBs. MIXDES 2017: 220-223 - Enrique P. Blair:
Quantum-Dot Cellular Automata: A Clocked Architecture for High-Speed, Energy-Efficient Molecular Computing. UCNC 2017: 56-68 - 2016
- Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara:
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2310-2319 (2016) - Liang Geng, Jizhong Shen, Congyuan Xu:
Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications. IET Comput. Digit. Tech. 10(4): 193-201 (2016) - Kyungho Ryu, Jiwan Jung, Dong-Hoon Jung, Jin Hyuk Kim, Seong-Ook Jung:
High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1484-1492 (2016) - Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte:
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. ATS 2016: 19-24 - Enkhbayasgalan Gantsog, Deyu Liu, Alyssa B. Apsel:
0.89 mW on-chip jitter-measurement circuit for high speed clock with sub-picosecond resolution. ESSCIRC 2016: 457-460 - Shi-Yu Huang, Tzu-Heng Huang, Kun-Han Tsai, Wu-Tung Cheng:
A wide-range clock signal generation scheme for speed grading of a logic core. HPCS 2016: 125-129 - Song Jia, Ziyi Wang, Zijin Li, Yuan Wang:
A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. ISCAS 2016: 2751-2754