- 2010
- Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu:
A Computation and Power Reduction Technique for H.264 Intra Prediction. DSD 2010: 753-760 - Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. DSD 2010: 3-10 - Luca Amati, Cristiana Bolchini, Fabio Salice, Federico Franzoso:
A Formal Condition to Stop an Incremental Automatic Functional Diagnosis. DSD 2010: 637-643 - Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors:
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. DSD 2010: 675-680 - Christiaan Baaij, Matthijs Kooijman, Jan Kuper, Arjan Boeijink, Marco Gerards:
C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell. DSD 2010: 714-721 - Elias Baaklini, Hassan Sbeity, Smaïl Niar, Nouhad Amaneddine:
H.264 Color Components Video Decoding Parallelization on Multi-core Processors. DSD 2010: 785-790 - Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiss, Josef Haid:
Automated Power Characterization for Run-Time Power Emulation of SoC Designs. DSD 2010: 587-594 - Dimitris Bakalis, Haridimos T. Vergos:
Area-Efficient Multi-moduli Squarers for RNS. DSD 2010: 408-411 - Jan Balach, Ondrej Novák:
Reconfigurable Fault-Tolerant System Sychronization. DSD 2010: 817-820 - Jiri Balcarek, Petr Fiser, Jan Schmidt:
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. DSD 2010: 805-808 - Enrique Barajas, Diego Mateo, José Luis González:
Behavioural Modelling of DLLs for Fast Simulation and Optimisation of Jitter and Power Consumption. DSD 2010: 541-547 - Majd Ghazi Batarseh, Ehab Shobaki, Xiang Fang, Haibing Hu, Issa Batarseh:
New Digital Control Technique for Improving Transient Response in DC - DC Converters. DSD 2010: 793-796 - Florent Berthelot, François Charot, Charles Wagner, Christophe Wolinski:
Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation. DSD 2010: 667-674 - Dennis Bode, Mladen Berekovic, Axel Borkowski, Ludger Buker:
QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration. DSD 2010: 141-146 - Jaroslav Borecký, Martin Kohlík, Hana Kubátová, Pavel Kubalík:
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication. DSD 2010: 380-386 - Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería:
Filtering Directory Lookups in CMPs. DSD 2010: 207-216 - Marcel D. van de Burgwal, Kenneth C. Rovers, Koen C. H. Blom, André B. J. Kokkeler, Gerard J. M. Smit:
Adaptive Beamforming Using the Reconfigurable MONTIUM TP. DSD 2010: 301-308 - Jing Cao, Albert Nymeyer:
A Markov Model for Low-Power High-Fidelity Design-Space Exploration. DSD 2010: 115-122 - Andrea Castagnetti, Cécile Belleudy, Sébastien Bilavarn, Michel Auguin:
Power Consumption Modeling for DVFS Exploitation. DSD 2010: 579-586 - Allen Chen, Ryan Hoppal, Tom Chen:
On CMOS Memory Design in Low Supply Voltage for Integrated Biosensor Applications. DSD 2010: 628-634 - Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. DSD 2010: 706-713 - Zhufei Chu, Yinshui Xia, William N. N. Hung, Lun-Yao Wang, Xiaoyu Song:
A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping. DSD 2010: 681-688 - Claas Cornelius, Philipp Gorski, Stephan Kubisch, Dirk Timmermann:
Trading Hardware Overhead for Communication Performance in Mesh-Type Topologies. DSD 2010: 173-180 - Giovanni Danese, Mauro Giachero, Francesco Leporati, Nelson Nazzicari:
A Multicore Embedded Processor for Fingerprint Recognition. DSD 2010: 779-784 - Julio Dondo, Fernando Rincón, Jesús Barba, Francisco Moya, Francisco Sánchez, Juan Carlos López:
Persistence Management Model for Dynamically Reconfigurable Hardware. DSD 2010: 482-489 - Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, Mehdi Baradaran Tahoori:
A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits. DSD 2010: 797-800 - Phillip David Ferguson, Aristides Efthymiou, Tughrul Arslan, Danny Hume:
Optimising Self-Timed FPGA Circuits. DSD 2010: 563-570 - Ronaldo Rodrigues Ferreira, Álvaro Freitas Moreira, Luigi Carro:
System Level Hardening by Computing with Matrices. DSD 2010: 373-379 - Pierfrancesco Foglia, Cosimo Antonio Prete, Marco Solinas, Giovanna Monni:
Re-NUCA: Boosting CMP Performance Through Block Replication. DSD 2010: 199-206 - Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: A Robustness Checker for Digital Circuits. DSD 2010: 226-231