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ORCIDHong Wang 0003
Person information
- affiliation: Intel Santa Clara, California
Other persons with the same name
- Hong Wang — disambiguation page
- Hong Wang 0001
![[0000-0003-1069-9786]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-1069-9786")
— Oak Ridge National Laboratory, Oak Ridge, TN, USA (and 7 more) - Hong Wang 0002 — University of Connecticut, Department of Computer Science and Engineering
- Hong Wang 0004 — Tsinghua University
- Hong Wang 0005 — University of Idaho, Department of Mathematics, Moscow, ID, USA (and 2 more)
- Hong Wang 0006 — Tohoku University
- Hong Wang 0007 — University of Toledo, Ohio, USA
- Hong Wang 0008 — Nanyang Technological University, Singapore
- Hong Wang 0009 — Central South University, School of Mathematics and Statistics, Changsha, China (and 1 more)
- Hong Wang 0010 — Northeastern University, Department of Mechanical Engineering and Automation, Shenyang, China (and 1 more)
- Hong Wang 0011 — City University of Hong Kong, State Key Laboratory of Millimeter Waves, Hong Kong (and 1 more)
- Hong Wang 0012 — Nanjing Audit University, Institute for Social and Economic Research, China (and 1 more)
- Hong Wang 0013 — Agriculture and Agri-Food Canada, Saskatchewan, Canada
- Hong Wang 0014 — Tsinghua University, Tsinghua Intelligent Vehicle Design and Safety Research Institute, Beijing, China (and 2 more)
- Hong Wang 0015 — Shandong Normal University, School of Information Science and Engineering, Jinan, China
- Hong Wang 0016 — Hong Kong Polytechnic University, Department of Mechanical Engineering, Hong Kong (and 1 more)
- Hong Wang 0017 — Air Force Engineering University, Information and Navigation College, Xi'an, China (and 1 more)
- Hong Wang 0018 — University of South Carolina, Department of Mathematics, USA
- Hong Wang 0019 — Qilu Hospital of Shandong University, Jinan, China
- Hong Wang 0020 — University of Greenwich, London, UK
- Hong Wang 0021 — Tencent Jarvis Lab, Shenzhen, China (and 1 more)
- Hong Wang 0022 — Beijing Normal University, Faculty of Geographical Science, State Key Laboratory of Earth Surface Processes and Resource Ecology, China
- Hong Wang 0023 — University of California, Santa Barbara, CA, USA
- Hong Wang 0024 — Brookhaven National Laboratory, NY, USA (and 1 more)
- Hong Wang 0025 — Beijing Institute of Technology, Key Laboratory of Photoelectronic Imaging Technology and System, Ministry of Education, China (and 1 more)
- Hong Wang 0026 — Shanxi Normal University, School of Mathematics and Computer Science, China
- Hong Wang 0027 — Henan Key Laboratory of Network Cryptography Technology, State Key Laboratory of Mathematical Engineering and Advanced Computing, Zhengzhou, China
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Journal Articles
- 2011
[j5]Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Hong Jiang, Guei-Yuan Lueh, Thomas Piazza, Hong Wang:
Bothnia: a dual-personality extension to the Intel integrated graphics driver. ACM SIGOPS Oper. Syst. Rev. 45(1): 11-20 (2011)- 2008
- [j4]Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen:
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Trans. Parallel Distributed Syst. 19(7): 914-925 (2008) - 2004
- [j3]Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen:
Helper Threads via Virtual Multithreading. IEEE Micro 24(6): 74-82 (2004) - 1997
- [j2]Hong Wang, Tong Sun, Qing Yang:
Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags. IEEE Trans. Computers 46(11): 1187-1201 (1997) - 1993
- [j1]Qing Yang, Hong Wang:
A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors. IEEE Trans. Parallel Distributed Syst. 4(10): 1165-1171 (1993)
Conference and Workshop Papers
- 2019
- [c36]Dipan Kumar Mandal, Srivatsava Jandhyala, Om Ji Omer, Gurpreet S. Kalsi, Biji George, Gopi Neela, Santhosh Kumar Rethinagiri, Sreenivas Subramoney, Lance Hacking, Jim Radford, Eagle Jones, Belliappa Kuttanna, Hong Wang:
Visual Inertial Odometry At the Edge: A Hardware-Software Co-design Approach for Ultra-low Latency and Power. DATE 2019: 960-963 - 2018
- [c35]Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, Hong Wang:
Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems. DAC 2018: 170:1-170:6 - [c34]Anant Nori, Jayesh Gaur, Siddharth Rai, Sreenivas Subramoney, Hong Wang:
Criticality Aware Tiered Cache Hierarchy: A Fundamental Relook at Multi-Level Cache Hierarchies. ISCA 2018: 96-109 - [c33]Kunal Korgaonkar, Ishwar Bhati, Huichu Liu, Jayesh Gaur, Sasikanth Manipatruni, Sreenivas Subramoney, Tanay Karnik, Steven Swanson, Ian Young, Hong Wang:
Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache. ISCA 2018: 315-327 - [c32]Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang:
Tackling memory access latency through DRAM row management. MEMSYS 2018: 137-147 - 2011
- [c31]Guilherme Ottoni, Gautham N. Chinya, Gerolf Hoflehner, Jamison D. Collins, Amit Kumar, Ethan Schuchman, David R. Ditzel, Ronak Singhal, Hong Wang:
AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs. Conf. Computing Frontiers 2011: 21 - [c30]Guilherme Ottoni, Thomas Hartin, Christopher T. Weaver, Jason Brandt, Belliappa Kuttanna, Hong Wang:
Harmonia: a transparent, efficient, and harmonious dynamic binary translator targeting the Intel® architecture. Conf. Computing Frontiers 2011: 26 - 2010
- [c29]Sung-Boem Park, Anne Bracy, Hong Wang, Subhasish Mitra:
BLoG: post-silicon bug localization in processors using bug localization graphs. DAC 2010: 368-373 - [c28]Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang:
Intel nehalem processor core made FPGA synthesizable. FPGA 2010: 3-12 - 2009
- [c27]Perry H. Wang, Jamison D. Collins, Christopher T. Weaver, Belliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang:
Intel® atomTM processor core made FPGA-synthesizable. FPGA 2009: 209-218 - [c26]Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh:
Criticality-based optimizations for efficient load processing. HPCA 2009: 419-430 - 2008
- [c25]Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang:
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. PACT 2008: 52-61 - [c24]Michael D. Linderman, Jamison D. Collins, Hong Wang, Teresa H. Meng:
Merge: a programming model for heterogeneous multi-core systems. ASPLOS 2008: 287-296 - [c23]Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz:
Processor Performance Modeling using Symbolic Simulation. ISPASS 2008: 127-138 - [c22]Benjamin C. Lee, Jamison D. Collins, Hong Wang, David M. Brooks:
CPR: Composable performance regression for scalable multiprocessor models. MICRO 2008: 270-281 - 2007
- [c21]Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Bernard Lint, Asit Mallick, Koichi Yamada, Hong Wang:
Sequencer virtualization. ICS 2007: 148-157 - [c20]Perry H. Wang, Jamison D. Collins, Gautham N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y. Yang, Guei-Yuan Lueh, Hong Wang:
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. PLDI 2007: 156-166 - 2006
- [c19]Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan N. Rakvic, Hong Wang, John Paul Shen:
Multiple Instruction Stream Processor. ISCA 2006: 114-127 - 2005
- [c18]Satish Narayanasamy, Hong Wang, Perry H. Wang, John Paul Shen, Brad Calder:
A Dependency Chain Clustered Microarchitecture. IPDPS 2005 - 2004
- [c17]Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen:
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. ASPLOS 2004: 144-155 - [c16]Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar, John Paul Shen:
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. CGO 2004: 27-38 - [c15]Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen:
Hardware Support for Prescient Instruction Prefetch. HPCA 2004: 84-95 - [c14]Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang:
Best of Both Latency and Throughput. ICCD 2004: 236-243 - [c13]Jamison D. Collins, Dean M. Tullsen, Hong Wang:
Control Flow Optimization Via Dynamic Reconvergence Prediction. MICRO 2004: 129-140 - 2003
- [c12]Hong Wang, Shiri Manor, Dave LaFollette, Nadav Nesher, Ku-jei King, Perry H. Wang, Shay Levy, Shai Satt, Gal Carmeli, Arjun Kapur, Ioannis Schoinas, Ed Rubinstein, Rahul Bhatt:
Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations. ISPASS 2003: 11-21 - [c11]Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen:
A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS 2003: 13-24 - 2002
- [c10]R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen:
Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. Interaction between Compilers and Computer Architectures 2002: 57-67 - [c9]Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen:
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. HPCA 2002: 187-196 - [c8]Shih-Wei Liao, Perry H. Wang, Hong Wang, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery:
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. PLDI 2002: 117-128 - 2001
- [c7]Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen:
Register Renaming and Scheduling for Dynamic Execution of Predicated Code. HPCA 2001: 15-25 - [c6]Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen:
Speculative precomputation: long-range prefetching of delinquent loads. ISCA 2001: 14-25 - [c5]Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen:
Dynamic speculative precomputation. MICRO 2001: 306-317 - 2000
- [c4]Thomas Y. Yeh, Hong Wang:
Redundant Arithmetic Optimizations (Research Note). Euro-Par 2000: 984-988 - 1995
- [c3]Hong Wang, Tong Sun, Qing Yang:
CAT - Caching Address Tags: A Technique for Reducing Area Cost of On-Chip Caches. ISCA 1995: 381-390 - 1992
- [c2]Qing Yang, Hong Wang:
On Fault-Tolerant Computation of Orthogonal Transforms on Hypercube Computers. ICPP (1) 1992: 253-256 - 1991
- [c1]Hong Wang, Qing Yang:
Prime Cube Graph Approach for Processor Allocation in Hypercube Multiprocessors. ICPP (1) 1991: 25-32
Informal and Other Publications
- 2018
- [i1]Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, Hong Wang:
MARS: Memory Aware Reordered Source. CoRR abs/1808.03518 (2018)
Coauthor Index
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