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ORCIDChaitanya Sathe
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Books and Theses
- 2014
[b1]Chaitanya Sathe:
Computational study of graphene nanopore sensor for DNA sensing. University of Illinois Urbana-Champaign, USA, 2014
Journal Articles
- 2010
- [j2]Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Mahesh B. Patil:
A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 627-631 (2010) - 2009
- [j1]Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini
, V. Ramgopal Rao, Mahesh B. Patil:
A Novel Table-Based Approach for Design of FinFET Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1061-1070 (2009)
Conference and Workshop Papers
- 2010
- [c3]Angada B. Sachid, Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao, Mahesh B. Patil:
Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework. ISQED 2010: 713-720 - 2009
- [c2]Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil:
Automated design and optimization of circuits in emerging technologies. ASP-DAC 2009: 504-509 - 2007
- [c1]Chaitanya Sathe, Santanu Mahapatra:
Modeling and Analysis of Noise Margin in SET Logic. VLSI Design 2007: 207-214
Coauthor Index
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