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Chun C. Lee
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Journal Articles
- 2023
- [j5]Amy Whitcombe
, Chun C. Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu
, Jaykant Timbadiya, Abhishek Agrawal
, Brent R. Carlton
, Peter Sagazio
, Stefano Pellerano, Christopher D. Hull:
A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW. IEEE J. Solid State Circuits 58(4): 972-982 (2023) - 2022
- [j4]Steven Callender
, Abhishek Agrawal
, Amy Whitcombe
, Ritesh Bhat
, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis
, Brent R. Carlton
, Christopher D. Hull, Stefano Pellerano:
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET. IEEE J. Solid State Circuits 57(12): 3582-3598 (2022) - 2013
- [j3]Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Khoa Minh Nguyen, Hyung-Jin Lee, Ashoke Ravi, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst
, Stefano Pellerano, Tong Kim, Satish Venkatesan, Durgesh Srivastava, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Sunder Ramamurthy, Raj Yavatkar, Krishnamurthy Soumyanath:
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver. IEEE J. Solid State Circuits 48(1): 91-103 (2013) - 2011
- [j2]Chun C. Lee, Michael P. Flynn:
A SAR-Assisted Two-Stage Pipeline ADC. IEEE J. Solid State Circuits 46(4): 859-869 (2011) - [j1]Chun C. Lee, Michael P. Flynn:
A 14 b 23 MS/s 48 mW Resetting Sigma Delta ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1167-1177 (2011)
Conference and Workshop Papers
- 2022
- [c6]Steven Callender, Amy Whitcombe, Abhishek Agrawal, Ritesh Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, Georgios C. Dogiamis, Brent R. Carlton, Mark Chakravorti, Stefano Pellerano, Christopher D. Hull:
A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology. ISSCC 2022: 78-80 - [c5]Amy Whitcombe, Chun C. Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent R. Carlton, Peter Sagazio, Stefano Pellerano, Christopher D. Hull:
A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW. VLSI Technology and Circuits 2022: 170-171 - 2021
- [c4]Hao Luo, Somnath Kundu, Chun C. Lee, Rinkle Jain, Sarah Shahraini, Eduardo Alban, Timo Huusari, Jason Mix, Nasser A. Kurd, Mohamed Abdel-moneum, Brent R. Carlton:
A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS. CICC 2021: 1-2 - 2015
- [c3]Chun C. Lee, Cho-Ying Lu, Ramya Narayanaswamy, Jad B. Rizk:
A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS. VLSIC 2015: 62- - 2012
- [c2]Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst
, Stefano Pellerano, Tong Kim, Durgesh Srivastava, Satish Venkatesan, Hyung-Jin Lee, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Krishnamurthy Soumyanath, Sunder Ramamurthy:
32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver. ISSCC 2012: 62-64 - [c1]Yulin Tan, Jon Duster, Chang-Tsung Fu, Erkan Alpman, Ajay Balankutty, Chun C. Lee, Ashoke Ravi, Stefano Pellerano, Kailash Chandrashekar, Hyung Seok Kim, Brent R. Carlton, Satoshi Suzuki, M. Shafi, Yorgos Palaskas, Hasnain Lakdawala:
A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS. VLSIC 2012: 76-77
Coauthor Index
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