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2020 – today
- 2022
[c21]Dongyoung Lee, Kyungsu Kang, Jongseong Park, Byunghoon Lee, Jinbeom Kim, Jae-Woo Im:
Toward Heterogeneous Virtual Platforms For Early SW Development. ISOCC 2022: 384-385- [c20]Minwoo Im, Kyungsu Kang, Heonyoung Yeom:
Accelerating RocksDB for small-zone ZNS SSDs by parallel I/O mechanism. Middleware Industry 2022: 15-21 - 2021
- [c19]Jungyun Choi, Kyungsu Kang, Byunghoon Lee, Sangho Park, Jae-Woo Im:
Early HW/SW Co-Verification Using Virtual Platforms. ISOCC 2021: 1-2 - 2020
- [c18]Jungyun Choi, Kyungsu Kang, Sangho Park, Seunghan Lee, YoHan Park, Byeongwook Bae, Byunghoon Lee, ByungChul Yoo:
On-chip Interconnect Optimization and Validation using Virtual Platform. ISOCC 2020: 53-54
2010 – 2019
- 2019
- [c17]Kyungsu Kang, Sangho Park, Byeongwook Bae, Jungyun Choi, SungGil Lee, Byunghoon Lee, Jong-Bae Lee:
Seamless SoC Verification Using Virtual Platforms: An Industrial Case Study. DATE 2019: 1204-1205 - 2016
- [j6]Seunghan Lee, Kyungsu Kang, Jongpil Jung, Chong-Min Kyung:
Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3118-3131 (2016) - [c16]Kyungsu Kang, Sangho Park, Jong-Bae Lee, Luca Benini, Giovanni De Micheli:
A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache. DATE 2016: 1465-1468 - 2015
- [j5]Jinho Lee
, Kyungsu Kang, Kiyoung Choi:
REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections. ACM J. Emerg. Technol. Comput. Syst. 12(3): 26:1-26:22 (2015) - [j4]Seunghan Lee, Kyungsu Kang, Chong-Min Kyung:
Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 520-533 (2015) - [j3]Kyungsu Kang, Luca Benini, Giovanni De Micheli:
Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1828-1841 (2015) - [c15]Jinho Lee, Junwhan Ahn, Kiyoung Choi, Kyungsu Kang:
THOR: Orchestrated thermal management of cores and networks in 3D many-core architectures. ASP-DAC 2015: 773-778 - 2014
- [c14]Kyungsu Kang, Giovanni De Micheli, Seunghan Lee, Chong-Min Kyung:
Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache. ISQED 2014: 163-170 - [c13]Seunghan Lee, Kyungsu Kang, Jongpil Jung, Chong-Min Kyung:
Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors. ISQED 2014: 197-204 - 2013
- [c12]Jongpil Jung, Kyungsu Kang, Giovanni De Micheli, Chong-Min Kyung:
Runtime 3-D stacked cache management for chip-multiprocessors. ISQED 2013: 68-72 - 2012
- [c11]Woojin Yun, Jongpil Jung, Kyungsu Kang, Chong-Min Kyung:
Temperature-aware energy minimization of 3D-stacked L2 DRAM cache through DVFS. ISOCC 2012: 475-478 - [c10]Jongpil Jung, Kyungsu Kang, Jae-Jin Lee, Youngjun Yoon, Chong-Min Kyung:
Cost-effective TSV redundancy configuration. VLSI-SoC 2012: 263-266 - [c9]Kyungsu Kang, Luca Benini, Giovanni De Micheli:
A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory. VLSI-SoC 2012: 283-286 - 2011
- [j2]Kyungsu Kang, Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung:
Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 905-918 (2011) - [c8]Jongpil Jung, Kyungsu Kang, Chong-Min Kyung:
Design and management of 3D-stacked NUCA cache for chip multiprocessors. ACM Great Lakes Symposium on VLSI 2011: 91-96 - [c7]Woojin Yun, Kyungsu Kang, Chong-Min Kyung:
Thermal-aware energy minimization of 3D-stacked L3 cache with error rate limitation. ISCAS 2011: 1672-1675 - [c6]Kyungsu Kang, Jongpil Jung, Sungjoo Yoo, Chong-Min Kyung:
Maximizing throughput of temperature-constrained multi-core systems with 3D-stacked cache memory. ISQED 2011: 577-582 - [c5]Asim Khan, Kyungsu Kang, Chong-Min Kyung:
Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache. VLSI-SoC 2011: 130-135 - 2010
- [j1]Kyungsu Kang, Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung:
Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks With Runtime Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1381-1394 (2010) - [c4]Seunghan Lee, Kyungsu Kang, Chong-Min Kyung:
Temperature- and bus traffic- aware data placement in 3D-stacked cache. VLSI-SoC 2010: 352-357
2000 – 2009
- 2007
- [c3]Kyungsu Kang, Jungsoo Kim, Heejun Shim, Chong-Min Kyung:
Software power estimation using IPI(inter-prefetch interval) power model for advanced off-the-shelf processor. ACM Great Lakes Symposium on VLSI 2007: 594-599 - [c2]Heejun Shim, Kyungsu Kang, Chong-Min Kyung:
Search Area Selective Reuse Algorithm in Motion Estimation. ICME 2007: 1611-1614 - [c1]Jungsoo Kim, Kyungsu Kang, Heejun Shim, Woong Hwangbo, Chong-Min Kyung:
Fast estimation of software energy consumption using IPI(Inter-Prefetch Interval) energy model. VLSI-SoC 2007: 224-229
Coauthor Index
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