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ORCIDKiyoo Itoh 0001
Person information
- affiliation: Hitachi, Ltd., Tokyo, Japan
Other persons with the same name
- Kiyoo Itoh 0002 — Institut supérieur d'électronique de Paris, Paris, France
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Books and Theses
- 2011
[b2]Masashi Horiguchi, Kiyoo Itoh:
Nanoscale Memory Repair. Integrated Circuits and Systems, Springer 2011, ISBN 978-1-4419-7957-5, pp. 1-215- 2007
- [b1]Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka:
Ultra-Low Voltage Nano-Scale Memories. Series on Integrated Circuits and Systems, Springer 2007, ISBN 978-0-387-33398-4, pp. 1-346
Journal Articles
- 2012
- [j15]Akira Kotabe, Kiyoo Itoh, Riichiro Takemura:
0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs. IEICE Trans. Electron. 95-C(4): 555-563 (2012) - [j14]Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh:
Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. IEICE Trans. Electron. 95-C(4): 594-599 (2012) - [j13]Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh:
A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. IEICE Trans. Electron. 95-C(4): 600-608 (2012) - 2011
- [j12]Kiyoo Itoh:
Embedded Memories: Progress and a Look into the Future. IEEE Des. Test Comput. 28(1): 10-13 (2011) - 2010
- [j11]Kiyoo Itoh, Masanao Yamaoka, Takashi Oshima
:
Adaptive Circuits for the 0.5-V Nanoscale CMOS Era. IEICE Trans. Electron. 93-C(3): 216-233 (2010) - 2008
- [j10]Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi:
Memory at VLSI Circuits Symposium. IEEE J. Solid State Circuits 43(4): 762-768 (2008) - 2007
- [j9]Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara:
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. IEICE Trans. Electron. 90-C(4): 758-764 (2007) - 2003
- [j8]Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh:
Review and future prospects of low-voltage RAM circuits. IBM J. Res. Dev. 47(5-6): 525-552 (2003) - 2002
- [j7]Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura:
A low-impedance open-bitline array for multigigabit DRAM. IEEE J. Solid State Circuits 37(4): 487-498 (2002) - 2001
- [j6]Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh:
A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. IEEE J. Solid State Circuits 36(11): 1721-1727 (2001) - 1997
- [j5]Kiyoo Itoh, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe:
Limitations and challenges of multigigabit DRAM chip design. IEEE J. Solid State Circuits 32(5): 624-634 (1997) - 1995
- [j4]Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome:
Trends in low-power RAM circuit technologies. Proc. IEEE 83(4): 524-543 (1995) - 1994
- [j3]Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Subthreshold-current reduction circuits for multi-gigabit DRAM's. IEEE J. Solid State Circuits 29(7): 761-769 (1994) - [j2]Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki:
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. IEEE J. Solid State Circuits 29(8): 887-894 (1994) - 1993
- [j1]Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito:
A single 1.5-V digital chip for a 106 synapse neural network. IEEE Trans. Neural Networks 4(3): 387-393 (1993)
Conference and Workshop Papers
- 2011
- [c17]Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi:
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC 2011: 1-7 - [c16]Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul:
Beyond the horizon: The next 10x reduction in power - Challenges and solutions. ISSCC 2011: 31 - 2010
- [c15]Kiyoo Itoh:
Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs. PATMOS 2010: 255 - 2009
- [c14]Kiyoo Itoh:
Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. ISLPED 2009: 273-274 - [c13]Kiyoo Itoh:
Adaptive circuits for the 0.5-V nanoscale CMOS era. ISSCC 2009: 14-20 - [c12]Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh:
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. ISSCC 2009: 142-143 - 2007
- [c11]Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka:
Low-voltage limitations of memory-rich nano-scale CMOS LSIs. ESSCIRC 2007: 68-75 - [c10]Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara:
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ACM Great Lakes Symposium on VLSI 2007: 529-533 - [c9]Kiyoo Itoh:
Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs. ICECS 2007: 1 - [c8]Kiyoo Itoh, Riichiro Takemura:
Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs. ICECS 2007: 739-742 - 2006
- [c7]Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara:
Ultra-low voltage nano-scale embedded RAMs. ISCAS 2006 - [c6]Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi:
A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers. ISLPED 2006: 123-126 - 2004
- [c5]Kiyoo Itoh, Kenichi Osada, Takayda Kawahara:
Reviews and future prospects of low-voltage embedded RAMs. CICC 2004: 339-344 - [c4]Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara:
Low-Voltage Embedded RAMs - Current Status and Future Trends. PATMOS 2004: 3-15 - 2002
- [c3]Kiyoo Itoh:
Low-voltage memories for power-aware systems. ISLPED 2002: 1-6 - [c2]Kiyoo Itoh:
Trends in Ultralow-Voltage RAM Technology. PATMOS 2002: 300-313 - 2001
- [c1]Kiyoo Itoh, Hiroyuki Mizuno:
Low-Voltage Embedded-RAM Technology: Present and Future. VLSI-SOC 2001: 277-288
Coauthor Index
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