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ORCIDXi Jin 0002
Person information
- affiliation: University of Science and Technology of China, State Key Laboratory of Particle Detection and Electronics, Institute of Microelectronics, Department of Physics, SoC Lab, Hefei, China
Other persons with the same name
- Xi Jin — disambiguation page
- Xi Jin 0001
![[0000-0002-1839-2714]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-1839-2714")
— Chinese Academy of Sciences, Shenyang Institute of Automation, Institutes for Robotics and Intelligent Manufacturing, China (and 1 more) - Xi Jin 0003 — Hubei University, Faculty of Mathematics and Statistics, Wuhan, China (and 1 more)
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2020 – today
- 2024
[c28]Qizhe Wu, Letian Zhao, Yuchen Gui, Huawen Liang, Xiaotian Wang, Xi Jin:
Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks. FPGA 2024: 187- [i4]Qizhe Wu, Yuchen Gui, Zhichen Zeng, Xiaotian Wang, Huawen Liang, Xi Jin:
EN-TensorCore: Advancing TensorCores Performance through Encoder-Based Methodology. CoRR abs/2404.11887 (2024) - 2023
- [j15]Ziqin Fan, Xi Jin:
Degree-Aware Graph Neural Network Quantization. Entropy 25(11): 1510 (2023) - [j14]Zerong He, Teng Tian, Qizhe Wu, Xi Jin:
FTW-GAT: An FPGA-Based Accelerator for Graph Attention Networks With Ternary Weights. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4211-4215 (2023) - [c27]Xiaotian Wang, Letian Zhao, Wei Wu, Xi Jin:
Dynamic Neural Network Accelerator for Multispectral detection Based on FPGA. ICACT 2023: 345-350 - [c26]Shuang Xue, Huawei Liang, Qizhe Wu, Xi Jin:
Scheduling Memory Access Optimization for HBM Based on CLOS. ICACT 2023: 448-453 - [c25]Xiaotian Wang, Letian Zhao, Wei Wu, Xi Jin:
MCANet: Multiscale Cross-Modality Attention Network for Multispectral Pedestrian Detection. MMM (1) 2023: 41-53 - 2022
- [j13]Teng Tian, Letian Zhao, Xiaotian Wang, Qizhe Wu, Wei Yuan, Xi Jin:
FP-GNN: Adaptive FPGA accelerator for Graph Neural Networks. Future Gener. Comput. Syst. 136: 294-310 (2022) - [j12]Wei Yuan, Teng Tian, Qizhe Wu, Xi Jin:
QEGCN: An FPGA-based accelerator for quantized GCNs with edge-level parallelism. J. Syst. Archit. 129: 102596 (2022) - [j11]Teng Tian, Xiaotian Wang, Letian Zhao, Wei Wu, Xuecang Zhang, Fangmin Lu, Tianqi Wang, Xi Jin:
G-NMP: Accelerating Graph Neural Networks with DIMM-based Near-Memory Processing. J. Syst. Archit. 129: 102602 (2022) - [j10]Letian Zhao, Rui Xu, Tianqi Wang, Teng Tian, Xiaotian Wang, Wei Wu, Chio-in Ieong, Xi Jin:
BaPipe: Balanced Pipeline Parallelism for DNN Training. Parallel Process. Lett. 32(3&4): 2250005:1-2250005:17 (2022) - [j9]Xiaotian Wang, Teng Tian, Letian Zhao, Wei Wu, Xi Jin:
Exploration of Balanced Design in Resource-Constrained Edge Device for Efficient CNNs. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4573-4577 (2022) - [c24]Wei Wu, Letian Zhao, Qizhe Wu, Xiaotian Wang, Teng Tian, Xi Jin:
An SSD-Based Accelerator for Singular Value Decomposition Recommendation Algorithm on Edge. HPEC 2022: 1-5 - [c23]Letian Zhao, Qizhe Wu, Xiaotian Wang, Teng Tian, Wei Wu, Xi Jin:
HuGraph: Acceleration of GCN Training on Heterogeneous FPGA Clusters with Quantization. HPEC 2022: 1-7 - [i3]Yuchen Gui, Boyi Wei, Wei Yuan, Xi Jin:
Hardware Acceleration of Sampling Algorithms in Sample and Aggregate Graph Neural Networks. CoRR abs/2209.02916 (2022) - 2021
- [j8]Rui Xu, Linfeng Tao, Tianqi Wang, Xi Jin, Chenxia Li, Zhengda Li, Jun Ren:
A hybrid precision low power computing-in-memory architecture for neural networks. Microprocess. Microsystems 80: 103351 (2021) - [c22]Qizhe Wu, Linfeng Tao, Huawen Liang, Wei Yuan, Teng Tian, Shuang Xue, Xi Jin:
Software-Hardware Co-Optimization on Partial-Sum Problem for PIM-based Neural Network Accelerator. HPEC 2021: 1-7 - [c21]Wei Yuan, Teng Tian, Huawen Liang, Xi Jin:
A Gather Accelerator for GNNs on FPGA Platform. ICPADS 2021: 74-81 - 2020
- [j7]Yuzhi Zhou, Xi Jin, Tianqi Wang:
FPGA Implementation of A∗ Algorithm for Real-Time Path Planning. Int. J. Reconfigurable Comput. 2020: 8896386:1-8896386:11 (2020) - [j6]Yuzhi Zhou, Xi Jin, Tian Xiang, Daolu Zha:
Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression. Microprocess. Microsystems 77: 103140 (2020) - [j5]Daolu Zha, Xi Jin, Rui Shang, Pengfei Yang:
A Real-Time Learning-Based Super-Resolution System on FPGA. Parallel Process. Lett. 30(4): 2050011:1-2050011:15 (2020) - [j4]Tianqi Wang, Tong Geng, Ang Li, Xi Jin, Martin C. Herbordt:
FPDeep: Scalable Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters. IEEE Trans. Computers 69(8): 1143-1158 (2020) - [c20]Yuzhi Zhou, Xi Jin, Tian Xiang:
RISC-V Graphics Rendering Instruction Set Extensions for Embedded AI Chips Implementation. BDET 2020: 85-88 - [c19]Teng Tian, Xi Jin, Letian Zhao, Xiaotian Wang, Jie Wang, Wei Wu:
Exploration of Memory Access Optimization for FPGA-based 3D CNN Accelerator. DATE 2020: 1650-1655 - [c18]Jie Wang, Xi Jin, Wei Wu:
TB-DNN: A Thin Binarized Deep Neural Network with High Accuracy. ICACT 2020: 419-424 - [i2]Letian Zhao, Rui Xu, Tianqi Wang, Teng Tian, Xiaotian Wang, Wei Wu, Chio-in Ieong, Xi Jin:
BaPipe: Exploration of Balanced Pipeline Parallelism for DNN Training. CoRR abs/2012.12544 (2020)
2010 – 2019
- 2019
- [c17]Tianqi Wang, Tong Geng, Xi Jin, Martin C. Herbordt:
Accelerating AP3M-Based Computational Astrophysics Simulations with Reconfigurable Clusters. ASAP 2019: 181-184 - [c16]Tianqi Wang, Tong Geng, Xi Jin, Martin C. Herbordt:
FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh Refinement Applications. FCCM 2019: 245-253 - [c15]Linfeng Tao, Rui Xu, Teng Tian, Zikun Xiang, Yifei Li, Xi Jin, Jun Ren, Zhengda Li, Chenxia Li:
CINT - An Energy-efficient Mixed-signal In-Memory CNN Accelerator Based on NOR Flash Memory. MobiSys 2019: 612-613 - [i1]Tong Geng, Tianqi Wang, Ang Li, Xi Jin, Martin C. Herbordt:
A Scalable Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Weight and Workload Balancing. CoRR abs/1901.01007 (2019) - 2018
- [j3]Shuaizhi Guo, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, Xi Jin:
RP-Ring: A Heterogeneous Multi-FPGA Accelerator. Int. J. Reconfigurable Comput. 2018 (2018) - [c14]Daolu Zha, Xi Jin, Rui Shang, Pengfei Yang:
A Real-Time Learning-Based Super-Resolution System Using Direct Simple Functions. ASAP 2018: 1-4 - [c13]Rui Xu, Xi Jin, Linfeng Tao, Shuaizhi Guo, Zikun Xiang, Teng Tian:
An efficient resource-optimized learning prefetcher for solid state drives. DATE 2018: 273-276 - [c12]Zikun Xiang, Tianqi Wang, Tong Geng, Tian Xiang, Xi Jin, Martin C. Herbordt:
Soft-Core. Multiple-Lane, FPGA-based ADCs for a Liquid Helium Environment. HPEC 2018: 1-6 - [c11]Shuaizhi Guo, Linlin Zheng, Xi Jin:
Accelerating a radio astronomy correlator on FPGA. ICACT 2018: 85-89 - [c10]Pengfei Yang, Daolu Zha, Xi Jin:
A pipelined division for fixed operation using user-defined floating point. ICACT 2018: 634-637 - 2017
- [c9]Teng Tian, Tianqi Wang, Xi Jin:
An Efficient Hardware Prefetcher Exploiting the Prefetch Potential of Long-Stride Access Pattern on Virtual Address. ISPA/IUCC 2017: 48-57 - 2016
- [j2]Bo Peng, Tianqi Wang, Xi Jin, Chuanjun Wang:
An Accelerating Solution for N-Body MOND Simulation with FPGA-SoC. Int. J. Reconfigurable Comput. 2016: 4592780:1-4592780:10 (2016) - [j1]Daolu Zha, Xi Jin, Tian Xiang:
A real-time global stereo-matching on FPGA. Microprocess. Microsystems 47: 419-428 (2016) - [c8]Tianqi Wang, Xi Jin, Bo Peng, Chuanjun Wang, Linlin Zheng:
RP-Ring: A Heterogeneous Multi-FPGA Accelerating Solution for N-Body Simulations. FCCM 2016: 31 - [c7]Daolu Zha, Xi Jin, Tian Xiang:
An Improved Global Stereo-Matching on FPGA for Real-Time Applications (Abstract Only). FPGA 2016: 274 - [c6]Tianqi Wang, Bo Peng, Xi Jin:
an Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation (Abstract Only). FPGA 2016: 277 - [c5]Bo Peng, Tianqi Wang, Xi Jin, Chuanjun Wang:
An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND (Abstract Only). FPGA 2016: 278 - [c4]Tianqi Wang, Linlin Zheng, Xi Jin, Bo Peng, Chuanjun Wang:
FPGA acceleration of TreePM N-body simulations for Modified Newton Dynamics. FPT 2016: 201-204 - [c3]Yuzhi Zhou, Xi Jin, Tian Xiang:
Fixed-ratio DXT format Frame Buffer Compressor for mobile graphics systems. FPT 2016: 273-276 - 2015
- [c2]Bo Peng, Xi Jin, Tianqi Wang, Xueliang Du:
Design of a Distributed Compressor for Astronomy SSD. FCCM 2015: 98 - 2014
- [c1]Tian Xiang, Lei Zhao, Xi Jin, Tianqi Wang, Shaoping Chu, Cong Ma, Shubin Liu, Qi An, Xue Ben:
A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES Architecture. FCCM 2014: 35
Coauthor Index
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last updated on 2024-06-03 02:53 CEST by the dblp team
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