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ORCIDMineo Kaneko
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2020 – today
- 2024
[j23]Saher Javaid, Mineo Kaneko
, Yasuo Tan:
Energy Balancing of Power System Considering Periodic Behavioral Pattern of Renewable Energy Sources and Demands. IEEE Access 12: 70245-70262 (2024)- [j22]Yuya Ushioda, Mineo Kaneko:
ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 600-609 (2024) - [c74]Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin:
Design Automation for Charge Recovery Logic. ISCAS 2024: 1-5 - 2023
- [j21]Akanit Kwangkaew, Siriya Skolthanarat, Chalie Charoenlarpnopparut, Mineo Kaneko:
Optimal Location and Sizing of Renewable Distributed Generators for Improving Robust Voltage Stability Against Uncontrollable Reactive Compensation. IEEE Access 11: 52260-52274 (2023) - [c73]Saher Javaid, Mineo Kaneko, Yasuo Tan:
Supply-Dominated Energy Balancing for Periodic Operation of Power System. ICCE-Taiwan 2023: 185-186 - [c72]Mineo Kaneko:
Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders. ISCAS 2023: 1-5 - 2022
- [c71]Yuya Ushioda, Mineo Kaneko:
Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem. ICCD 2022: 394-397 - [c70]Saher Javaid, Mineo Kaneko, Yasuo Tan, Nouman Ashraf:
LP-based Co-optimization of Power Generators and Power Storage Systems under the Condition of Safe Operation. ICCE-TW 2022: 575-576 - [c69]Tomohiro Noguchi, Omran Hindawi, Mineo Kaneko:
Three-Dimensional Flexible-Module Placement for Stacked Three-Dimensional Integration. ISCAS 2022: 3260-3264 - 2021
- [c68]Saher Javaid, Mineo Kaneko, Yasuo Tan:
Storage Minimization Considering System Conditions of Power Flow System. ICCE-TW 2021: 1-2 - [c67]Mineo Kaneko:
Minimum Structural Transformation in Parallel Prefix Adders and its Application to Search-Based Optimization. ISCAS 2021: 1-5 - 2020
- [j20]Masato Tatsuoka, Mineo Kaneko:
High Level Congestion Detection from C/C++ Source Code for High Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(12): 1437-1446 (2020) - [c66]Saher Javaid, Mineo Kaneko, Yasuo Tan:
System Condition for Controllable Power Flow System Considering Reaction Delay. ICCE-TW 2020: 1-2 - [c65]Mineo Kaneko:
Insertion-Based Procedural Construction and Optimization of Parallel Prefix Adders. ISCAS 2020: 1-5 - [c64]Mineo Kaneko:
Two-Graph Approach to Temperature Dependent Skew Scheduling. ISQED 2020: 432-437
2010 – 2019
- 2019
- [c63]Saher Javaid, Mineo Kaneko, Yasuo Tan:
A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices. GCCE 2019: 96-99 - [c62]Saher Javaid, Mineo Kaneko, Yasuo Tan:
Power Flow Management for Smart Grids: Considering Renewable Energy and Demand Uncertainty. ICCE-TW 2019: 1-2 - [c61]Mineo Kaneko:
A Novel Framework for Procedural Construction of Parallel Prefix Adders. ISCAS 2019: 1-5 - 2018
- [j19]Mineo Kaneko:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1000-1001 (2018) - [c60]Masato Tatsuoka, Mineo Kaneko:
Wire congestion aware high level synthesis flow with source code compiler. ICICDT 2018: 101-104 - [c59]Takayuki Moto, Mineo Kaneko:
Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing. ISCAS 2018: 1-5 - 2017
- [j18]Junghoon Oh, Mineo Kaneko:
Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1506-1510 (2017) - [j17]Mineo Kaneko:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2740 (2017) - [c58]Mineo Kaneko:
KKT-condition inspired solution of DVFS with limited number of voltage levels. ISCAS 2017: 1-4 - [c57]Mineo Kaneko:
Margin aware timing test and tuning algorithm for post-silicon skew tuning. MWSCAS 2017: 1244-1247 - [c56]Renyuan Zhang, Mineo Kaneko:
A random access analog memory with master-slave structure for implementing hexadecimal logic. SoCC 2017: 7-11 - 2016
- [j16]Junghoon Oh, Mineo Kaneko:
Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1311-1322 (2016) - [c55]Junghoon Oh, Mineo Kaneko:
Mixed error correction scheme and its design optimization for soft-error tolerant datapaths. APCCAS 2016: 362-365 - [c54]Mineo Kaneko:
KKT-condition based study on DVFS for heterogeneous task set. APCCAS 2016: 717-720 - [c53]Renyuan Zhang, Mineo Kaneko:
A 16-valued logic FPGA architecture employing analog memory circuit. ISCAS 2016: 718-721 - [c52]Junghoon Oh, Mineo Kaneko:
Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components. ISVLSI 2016: 595-600 - 2015
- [j15]Renyuan Zhang, Mineo Kaneko:
Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism. ACM Trans. Design Autom. Electr. Syst. 20(4): 64:1-64:19 (2015) - [c51]Mineo Kaneko:
A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling. ACM Great Lakes Symposium on VLSI 2015: 367-372 - [c50]Junghoon Oh, Mineo Kaneko:
Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis. ISCAS 2015: 49-52 - [c49]Renyuan Zhang, Mineo Kaneko:
A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism. ISCAS 2015: 942-945 - [c48]Keisuke Inoue, Mineo Kaneko:
Bitwidth-aware register allocation and binding for clock period minimization. MWSCAS 2015: 1-4 - 2014
- [c47]Renyuan Zhang, Mineo Kaneko:
A feasibility study on robust programmable delay element design based on neuron-MOS mechanism. ACM Great Lakes Symposium on VLSI 2014: 21-26 - [c46]Mineo Kaneko:
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract]. ACM Great Lakes Symposium on VLSI 2014: 91-92 - [c45]Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko:
An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops 2014: 251-256 - [c44]Mineo Kaneko, Yutaka Tsuboishi:
Constrained binding and scheduling of triplicated algorithm for fault tolerant datapath synthesis. ISCAS 2014: 1448-1451 - [c43]Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim:
Priority based maximum consuming power control in smart homes. ISGT 2014: 1-5 - 2013
- [j14]Keisuke Inoue, Mineo Kaneko:
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(8): 1712-1722 (2013) - [j13]Keisuke Inoue, Mineo Kaneko:
Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2689-2697 (2013) - 2012
- [j12]Keisuke Inoue, Mineo Kaneko:
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2330-2337 (2012) - [c42]Keisuke Inoue, Mineo Kaneko:
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range. ASP-DAC 2012: 239-244 - [c41]Keisuke Inoue, Mineo Kaneko:
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis. ACM Great Lakes Symposium on VLSI 2012: 79-82 - [c40]Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu:
An efficient approach for designing and minimizing reversible programmable logic arrays. ACM Great Lakes Symposium on VLSI 2012: 215-220 - [c39]Mineo Kaneko:
Timing-test scheduling for constraint-graph based post-silicon skew tuning. ICCD 2012: 460-465 - [c38]Mineo Kaneko, Jian Li:
Post-silicon skew tuning algorithm utilizing setup and hold timing tests. ISCAS 2012: 125-128 - [c37]Keisuke Inoue, Mineo Kaneko:
Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis. ISCAS 2012: 1664-1667 - [c36]Keisuke Inoue, Mineo Kaneko:
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis. ISQED 2012: 778-783 - [c35]Keisuke Inoue, Mineo Kaneko:
Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis. MWSCAS 2012: 631-634 - 2011
- [j11]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(4): 1067-1081 (2011) - [j10]Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko:
Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2563-2570 (2011) - [j9]Keisuke Inoue, Mineo Kaneko:
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. Inf. Media Technol. 6(4): 1103-1115 (2011) - [j8]Keisuke Inoue, Mineo Kaneko:
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. IPSJ Trans. Syst. LSI Des. Methodol. 4: 232-244 (2011) - [c34]Mineo Kaneko, Keisuke Inoue:
Ordered coloring-based resource binding for datapaths with improved skew-adjustability. ACM Great Lakes Symposium on VLSI 2011: 307-312 - [c33]Keisuke Inoue, Mineo Kaneko:
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis. ISCAS 2011: 550-553 - [c32]Mineo Kaneko:
A complete framework of simultaneous functional unit and register binding with skew scheduling. ISQED 2011: 189-195 - [c31]Keisuke Inoue, Mineo Kaneko:
Early planning for RT-level delay insertion during clock skew-aware register binding. VLSI-SoC 2011: 154-159 - 2010
- [c30]Keisuke Inoue, Mineo Kaneko:
Optimal register assignment with minimum-delay compensation for latch-based design. APCCAS 2010: 887-890 - [c29]Tsuyoshi Iwagaki, Mineo Kaneko:
A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties. DELTA 2010: 293-296 - [c28]Keisuke Inoue, Mineo Kaneko:
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. ACM Great Lakes Symposium on VLSI 2010: 111-114
2000 – 2009
- 2009
- [j7]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1096-1105 (2009) - [c27]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Safe clocking for the setup and hold timing constraints in datapath synthesis. ACM Great Lakes Symposium on VLSI 2009: 27-32 - [c26]Takayuki Obata, Mineo Kaneko:
Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis. ISCAS 2009: 1521-1524 - [c25]Tsuyoshi Iwagaki, Mineo Kaneko:
On the derivation of a minimum test set in high quality transition testing. LATW 2009: 1-6 - 2008
- [j6]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1044-1053 (2008) - [j5]Takayuki Obata, Mineo Kaneko:
Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3585-3595 (2008) - [c24]Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki:
Safe clocking register assignment in datapath synthesis. ICCD 2008: 120-127 - [c23]Takayuki Obata, Mineo Kaneko:
Concurrent skew and control step assignments in RT-level datapath synthesis. ISCAS 2008: 2018-2021 - 2007
- [j4]Koji Ohashi, Mineo Kaneko:
Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(3): 659-669 (2007) - [c22]Koji Ohashi, Mineo Kaneko:
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath. ACM Great Lakes Symposium on VLSI 2007: 481-484 - [c21]Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara:
Efficient path delay test generation based on stuck-at test generation using checker circuitry. ICCAD 2007: 418-423 - 2006
- [c20]Mineo Kaneko:
Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules. APCCAS 2006: 335-338 - 2005
- [c19]Koji Ohashi, Mineo Kaneko:
Statistical Analysis Driven Synthesis of Asynchronous Systems. ICCD 2005: 200-205 - [c18]Koji Ohashi, Mineo Kaneko:
Statistical schedule length analysis in asynchronous datapath synthesis. ISCAS (1) 2005: 700-703 - 2003
- [c17]Mineo Kaneko, Kazuaki Oshio:
Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism. ISCAS (5) 2003: 645-648 - 2002
- [j3]Toshiyuki Yorozuya, Koji Ohashi, Mineo Kaneko:
Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 819-826 (2002) - [j2]Satoshi Tayu, Mineo Kaneko:
Characterization and Computation of Steiner Routing Based on Elmore's Delay Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2764-2774 (2002) - [c16]Satoshi Tayu, Mineo Kaneko:
Characterization and computation of Steiner wiring based on Elmore's delay model. APCCAS (2) 2002: 335-340 - [c15]Yasuhiro Takashima, Akira Kaneko, Shinji Sato, Mineo Kaneko:
Two-dimensional placement method based on divide-and-replacement. APCCAS (2) 2002: 341-346 - [c14]Mineo Kaneko, Jun'ichi Yokoyama, Satoshi Tayu:
3D scheduling based on code space exploration for dynamically reconfigurable systems. ISCAS (5) 2002: 465-468 - [c13]Koji Ohashi, Mineo Kaneko:
Heuristic assignment-driven scheduling for data-path synthesis. ISCAS (4) 2002: 703-706 - 2001
- [c12]Mineo Kaneko, Yasuaki Maekawa:
Extended dimensional threshold filtering-a bridge between FIR filter and median type filter. ISCAS (2) 2001: 309-312 - 2000
- [c11]Koji Ohashi, Mineo Kaneko, Satoshi Tayu:
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis. ICCD 2000: 370-375 - [c10]Mineo Kaneko, Yoshitaka Nishio, Satoshi Tayu:
Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications. ISCAS 2000: 57-60 - [c9]Choon-Sik Park, Mineo Kaneko:
An efficient scheme based on EMPDC graph model in synthesizing fault tolerant FIR filter. ISCAS 2000: 253-256 - [c8]Satoshi Tayu, Motoyasu Katsura, Mineo Kaneko:
An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays. ISPAN 2000: 114-120
1990 – 1999
- 1999
- [c7]Mineo Kaneko:
Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power. ISCAS (1) 1999: 262-265 - 1998
- [j1]Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko:
VLSI/PCB placement with obstacles based on sequence pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 60-68 (1998) - 1997
- [c6]Fernando Gil Vianna Resende Jr., Paulo S. R. Diniz, Mineo Kaneko, Akinori Nishihara:
Adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error with variable forgetting factors. ICASSP 1997: 2293-2296 - [c5]Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko:
VLSI/PCB placement with obstacles based on sequence-pair. ISPD 1997: 26-31 - 1994
- [c4]Sarwono Sutikno, Mineo Kaneko, Mahoki Onoda:
A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach. ISCAS 1994: 67-70 - [c3]Mineo Kaneko, Kazuhiro Sakaguchi:
Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model. ISCAS 1994: 93-96 - [c2]Fernando Gil Resende, Keiichi Tokuda, Mineo Kaneko:
AR Spectrum Estimation Based on Wavelet Representation. ISCAS 1994: 625-628 - 1993
- [c1]Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi:
A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits. ISCAS 1993: 2094-2097
Coauthor Index
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last updated on 2024-09-02 01:02 CEST by the dblp team
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