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ORCIDDaniel Sánchez 0003
Person information
- affiliation: MIT CSAIL, Cambridge, MA, USA
- affiliation (former): Stanford University, CA, USA
Other persons with the same name
- Daniel Sánchez 0001
![[0000-0002-6048-3994]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-6048-3994")
— University of Granada, Department of Computer Science and Artificial Intelligence, Spain - Daniel Sánchez Morillo (aka: Daniel Sánchez 0002) — University of Cadiz, Biomedical Engineering and Telemedicine Research Group, Spain
- Daniel Sánchez 0004 — University of Murcia, Spain
- Daniel Sánchez 0005 (aka: Daniel Sánchez Abril) — Universitat de Barcelona, Spain
- Daniel Sánchez 0006 — SRI International, Menlo Park, CA, USA
- Daniel Sánchez 0007 — Northwestern University, Evanston, IL, USA
- Daniel Sánchez 0008 — Florida International University, Miami, FL, USA
- Daniel Sánchez 0009 — Universidad de Valencia, Spain
- Daniel Sánchez 0010 — University of Puerto Rico
- Daniel Sánchez 0011 (aka: Daniel Sánchez Aranguren) — Osaka University, School of Engineering Science, Japan
- Daniel Sánchez 0012 — Universidad Distrital Francisco Jose de Caldas, Bogotá, Colombia
- Daniel Sánchez 0013 — Laboratorio de Circuitos y Sistemas Robustos (LCSR), Córdoba, Argentina
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Journal Articles
- 2024
[j10]Aleksandar Krastev, Nikola Samardzic, Simon Langowski, Srinivas Devadas, Daniel Sánchez:
A Tensor Compiler with Automatic Data Packing for Simple and Efficient Fully Homomorphic Encryption. Proc. ACM Program. Lang. 8(PLDI): 126-150 (2024)- 2022
- [j9]Axel Feldmann, Nikola Samardzic, Aleksandar Krastev, Srinivas Devadas, Ronald G. Dreslinski, Chris Peikert, Daniel Sánchez:
An Architecture to Accelerate Computation on Encrypted Data. IEEE Micro 42(4): 59-68 (2022) - 2021
- [j8]Po-An Tsai, Andrés Sánchez, Christopher W. Fletcher, Daniel Sánchez:
Leaking Secrets Through Compressed Caches. IEEE Micro 41(3): 27-33 (2021) - 2018
- [j7]Guowei Zhang, Daniel Sánchez:
Leveraging Hardware Caches for Memoization. IEEE Comput. Archit. Lett. 17(1): 59-63 (2018) - [j6]Xiangyao Yu, Yu Xia, Andrew Pavlo, Daniel Sánchez, Larry Rudolph, Srinivas Devadas:
Sundial: Harmonizing Concurrency Control and Caching in a Distributed OLTP Database Management System. Proc. VLDB Endow. 11(10): 1289-1302 (2018) - [j5]Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sánchez, Donghoon Yoo, Soojung Ryu:
Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems. ACM Trans. Archit. Code Optim. 15(1): 10:1-10:23 (2018) - 2017
- [j4]Nathan Beckmann, Daniel Sánchez:
Cache Calculus: Modeling Caches through Differential Equations. IEEE Comput. Archit. Lett. 16(1): 1-5 (2017) - 2016
- [j3]Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez:
Unlocking Ordered Parallelism with the Swarm Architecture. IEEE Micro 36(3): 105-117 (2016) - 2012
- [j2]Daniel Sánchez, Christos Kozyrakis:
Scalable and Efficient Fine-Grained Cache Partitioning with Vantage. IEEE Micro 32(3): 26-37 (2012) - 2010
- [j1]Daniel Sánchez, George Michelogiannakis, Christos Kozyrakis:
An analysis of on-chip interconnection networks for large-scale chip multiprocessors. ACM Trans. Archit. Code Optim. 7(1): 4:1-4:28 (2010)
Conference and Workshop Papers
- 2024
- [c59]Nikola Samardzic, Daniel Sánchez:
BitPacker: Enabling High Arithmetic Efficiency in Fully Homomorphic Encryption Accelerators. ASPLOS (2) 2024: 137-150 - [c58]Yifan Yang, Joel S. Emer, Daniel Sánchez:
Trapezoid: A Versatile Accelerator for Dense and Sparse Matrix Multiplications. ISCA 2024: 931-945 - 2023
- [c57]Yifan Yang, Joel S. Emer, Daniel Sánchez:
ISOSceles: Accelerating Sparse CNNs through Inter-Layer Pipelining. HPCA 2023: 598-610 - [c56]Quan M. Nguyen, Daniel Sánchez:
Phloem: Automatic Acceleration of Irregular Applications with Fine-Grain Pipeline Parallelism. HPCA 2023: 1262-1274 - [c55]Axel Feldmann, Daniel Sánchez:
Spatula: A Hardware Accelerator for Sparse Matrix Factorization. MICRO 2023: 91-104 - [c54]Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, Joel S. Emer, Daniel Sánchez:
Accelerating RTL Simulation with Hardware-Software Co-Design. MICRO 2023: 153-166 - 2022
- [c53]Srinivas Devadas, Simon Langowski, Nikola Samardzic, Sacha Servan-Schreiber, Daniel Sánchez:
Designing Hardware for Cryptography and Cryptography for Hardware. CCS 2022: 1-4 - [c52]Nikola Samardzic, Axel Feldmann, Aleksandar Krastev, Nathan Manohar, Nicholas Genise, Srinivas Devadas, Karim Eldefrawy, Chris Peikert, Daniel Sánchez:
CraterLake: a hardware accelerator for efficient unbounded computation on encrypted data. ISCA 2022: 173-187 - [c51]Hyun Ryong Lee, Daniel Sánchez:
Datamime: Generating Representative Benchmarks by Automatically Synthesizing Datasets. MICRO 2022: 1144-1159 - 2021
- [c50]Guowei Zhang, Nithya Attaluri, Joel S. Emer, Daniel Sánchez:
Gamma: leveraging Gustavson's algorithm to accelerate sparse matrix multiplication. ASPLOS 2021: 687-701 - [c49]Ajay Brahmakshatriya, Emily Furst, Victor A. Ying, Claire Hsu, Changwan Hong, Max Ruttenberg, Yunming Zhang, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Julian Shun, Mark Oskin, Daniel Sánchez, Saman P. Amarasinghe:
Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures. ISCA 2021: 429-442 - [c48]Yifan Yang, Joel S. Emer, Daniel Sánchez:
SpZip: Architectural Support for Effective Data Compression In Irregular Applications. ISCA 2021: 1069-1082 - [c47]Nikola Samardzic, Axel Feldmann, Aleksandar Krastev, Srinivas Devadas, Ronald G. Dreslinski, Christopher Peikert, Daniel Sánchez:
F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption. MICRO 2021: 238-252 - [c46]Quan M. Nguyen, Daniel Sánchez:
Fifer: Practical Acceleration of Irregular Applications on Reconfigurable Architectures. MICRO 2021: 1064-1077 - 2020
- [c45]Elliot Lockerman, Axel Feldmann, Mohammad Bakhshalipour, Alexandru Stanescu, Shashwat Gupta, Daniel Sánchez, Nathan Beckmann:
Livia: Data-Centric Computing Throughout the Memory Hierarchy. ASPLOS 2020: 417-433 - [c44]Po-An Tsai, Andrés Sánchez, Christopher W. Fletcher, Daniel Sánchez:
Safecracker: Leaking Secrets through Compressed Caches. ASPLOS 2020: 1125-1140 - [c43]Maleen Abeydeera, Daniel Sánchez:
Chronos: Efficient Speculative Parallelism for Accelerators. ASPLOS 2020: 1247-1262 - [c42]Victor A. Ying, Mark C. Jeffrey, Daniel Sánchez:
T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware. ISCA 2020: 159-172 - [c41]Quan M. Nguyen, Daniel Sánchez:
Pipette: Improving Core Utilization on Irregular Applications through Intra-Core Pipeline Parallelism. MICRO 2020: 596-608 - 2019
- [c40]Po-An Tsai, Daniel Sánchez:
Compress Objects, Not Cache Lines: An Object-Based Compressed Memory Hierarchy. ASPLOS 2019: 229-242 - [c39]Guowei Zhang, Daniel Sánchez:
Leveraging Caches to Accelerate Hash Tables and Memoization. MICRO 2019: 440-452 - [c38]Anurag Mukkara, Nathan Beckmann, Daniel Sánchez:
PHI: Architectural Support for Synchronization- and Bandwidth-Efficient Commutative Scatter Updates. MICRO 2019: 1009-1022 - 2018
- [c37]Nosayba El-Sayed, Anurag Mukkara, Po-An Tsai, Harshad Kasture, Xiaosong Ma, Daniel Sánchez:
KPart: A Hybrid Cache Partitioning-Sharing Technique for Commodity Multicores. HPCA 2018: 104-117 - [c36]Anurag Mukkara, Nathan Beckmann, Maleen Abeydeera, Xiaosong Ma, Daniel Sánchez:
Exploiting Locality in Graph Analytics through Hardware-Accelerated Traversal Scheduling. MICRO 2018: 1-14 - [c35]Po-An Tsai, Yee Ling Gan, Daniel Sánchez:
Rethinking the Memory Hierarchy for Modern Languages. MICRO 2018: 203-216 - [c34]Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel S. Emer, Daniel Sánchez:
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism. MICRO 2018: 217-230 - [c33]Po-An Tsai, Changping Chen, Daniel Sánchez:
Adaptive Scheduling for Systems with Asymmetric Memory Hierarchies. MICRO 2018: 641-654 - 2017
- [c32]Maleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey, Joel S. Emer, Daniel Sánchez:
SAM: Optimizing Multithreaded Cores for Speculative Parallelism. PACT 2017: 64-78 - [c31]Harshad Kasture, Xu Ji, Nosayba El-Sayed, Nathan Beckmann, Xiaosong Ma, Daniel Sánchez:
POSTER: Improving Datacenter Efficiency Through Partitioning-Aware Scheduling. PACT 2017: 134-135 - [c30]Po-An Tsai, Nathan Beckmann, Daniel Sánchez:
Nexus: A New Approach to Replication in Distributed Shared Caches. PACT 2017: 166-179 - [c29]Nathan Beckmann, Daniel Sánchez:
Maximizing Cache Performance Under Uncertainty. HPCA 2017: 109-120 - [c28]Sabrina M. Neuman, Jason E. Miller, Daniel Sánchez, Srinivas Devadas:
Using Application-Level Thread Progress Information to Manage Power and Performance. ICCD 2017: 501-508 - [c27]Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel S. Emer, Daniel Sánchez:
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism. ISCA 2017: 587-599 - [c26]Po-An Tsai, Nathan Beckmann, Daniel Sánchez:
Jenga: Software-Defined Cache Hierarchies. ISCA 2017: 652-665 - [c25]Xu Ji, Chao Wang, Nosayba El-Sayed, Xiaosong Ma, Youngjae Kim, Sudharshan S. Vazhkudai, Wei Xue, Daniel Sánchez:
Understanding object-level memory access patterns across the spectrum. SC 2017: 25 - 2016
- [c24]Anurag Mukkara, Nathan Beckmann, Daniel Sánchez:
Whirlpool: Improving Dynamic Cache Management with Static Data Classification. ASPLOS 2016: 113-127 - [c23]Nathan Beckmann, Daniel Sánchez:
Modeling cache performance beyond LRU. HPCA 2016: 225-236 - [c22]Harshad Kasture, Daniel Sánchez:
Tailbench: a benchmark suite and evaluation methodology for latency-critical applications. IISWC 2016: 3-12 - [c21]Mark C. Jeffrey, Suvinay Subramanian, Maleen Abeydeera, Joel S. Emer, Daniel Sánchez:
Data-centric execution of speculative parallel programs. MICRO 2016: 5:1-5:13 - [c20]Guowei Zhang, Virginia Chiu, Daniel Sánchez:
Exploiting semantic commutativity in hardware speculation. MICRO 2016: 34:1-34:12 - [c19]Xiangyao Yu, Andrew Pavlo, Daniel Sánchez, Srinivas Devadas:
TicToc: Time Traveling Optimistic Concurrency Control. SIGMOD Conference 2016: 1629-1642 - 2015
- [c18]Christina Delimitrou, Daniel Sánchez, Christos Kozyrakis:
Tarcil: reconciling scheduling speed and quality in large shared clusters. SoCC 2015: 97-110 - [c17]Nathan Beckmann, Daniel Sánchez:
Talus: A simple way to remove cliffs in cache performance. HPCA 2015: 64-75 - [c16]Nathan Beckmann, Po-An Tsai, Daniel Sánchez:
Scaling distributed cache hierarchies through computation and data co-scheduling. HPCA 2015: 538-550 - [c15]Guowei Zhang, Webb Horn, Daniel Sánchez:
Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems. MICRO 2015: 13-25 - [c14]Mark C. Jeffrey, Suvinay Subramanian, Cong Yan, Joel S. Emer, Daniel Sánchez:
A scalable architecture for ordered parallelism. MICRO 2015: 228-241 - [c13]Harshad Kasture, Davide B. Bartolini, Nathan Beckmann, Daniel Sánchez:
Rubik: fast analytical power management for latency-critical systems. MICRO 2015: 598-610 - [c12]Daniel Sánchez:
A scalable architecture for ordered irregular parallelism. IA3@SC 2015: 2:1 - 2014
- [c11]Harshad Kasture, Daniel Sánchez:
Ubik: efficient cache sharing with strict qos for latency-critical workloads. ASPLOS 2014: 729-742 - 2013
- [c10]Nathan Beckmann, Daniel Sánchez:
Jigsaw: Scalable software-defined caches. PACT 2013: 213-224 - [c9]Daniel Sánchez, Christos Kozyrakis:
ZSim: fast and accurate microarchitectural simulation of thousand-core systems. ISCA 2013: 475-486 - 2012
- [c8]Daniel Sánchez, Christos Kozyrakis:
SCD: A scalable coherence directory with flexible sharer set encoding. HPCA 2012: 129-140 - 2011
- [c7]Daniel Sánchez, David Lo, Richard M. Yoo, Jeremy Sugerman, Christos Kozyrakis:
Dynamic Fine-Grain Scheduling of Pipeline Parallelism. PACT 2011: 22-32 - [c6]Daniel Sánchez, Christos Kozyrakis:
A few ways can take you a long way: Efficient and highly associative caches with scalable partitioning for many-core CMPs. Hot Chips Symposium 2011: 1 - [c5]Daniel Sánchez, Christos Kozyrakis:
Vantage: scalable and efficient fine-grain cache partitioning. ISCA 2011: 57-68 - 2010
- [c4]Daniel Sánchez, Richard M. Yoo, Christos Kozyrakis:
Flexible architectural support for fine-grain scheduling. ASPLOS 2010: 311-322 - [c3]Daniel Sánchez, Christos Kozyrakis:
The ZCache: Decoupling Ways and Associativity. MICRO 2010: 187-198 - [c2]George Michelogiannakis, Daniel Sánchez, William J. Dally, Christos Kozyrakis:
Evaluating Bufferless Flow Control for On-chip Networks. NOCS 2010: 9-16 - 2007
- [c1]Daniel Sánchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam:
Implementing Signatures for Transactional Memory. MICRO 2007: 123-133
Editorship
- 2017
- [e1]Hillery C. Hunter, Jaime Moreno, Joel S. Emer, Daniel Sánchez:
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017. ACM 2017, ISBN 978-1-4503-4952-9 [contents]
Informal and Other Publications
- 2021
- [i2]Axel Feldmann, Nikola Samardzic, Aleksandar Krastev, Srini Devadas, Ronald G. Dreslinski, Karim Eldefrawy, Nicholas Genise, Chris Peikert, Daniel Sánchez:
F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption (Extended Version). CoRR abs/2109.05371 (2021) - 2016
- [i1]Sizhuo Zhang, Andrew Wright, Daniel Sánchez, Arvind:
Validating Simplified Processor Models in Architectural Studies. CoRR abs/1610.02094 (2016)
Coauthor Index
aka: Christos Kozyrakis
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