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ORCIDMasayuki Miyama
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2020 – today
- 2022
[j19]Masayuki Miyama:
FPGA Implementation of 3-Bit Quantized Multi-Task CNN for Contour Detection and Disparity Estimation. IEICE Trans. Inf. Syst. 105-D(2): 406-414 (2022)
2010 – 2019
- 2019
- [c9]Masayuki Miyama:
HD 180 FPS FPGA Processor to Generate Depth Image with Clear Object Boundary. ISDCS 2019: 1-4 - 2017
- [c8]Masayuki Miyama:
Fast stereo matching with super-pixels using one-way check and score filter. ICCSCE 2017: 278-283 - 2014
- [j18]Shunji Nakata
, Hiroshi Makino, Ryota Honda, Masayuki Miyama, Yoshio Matsuda:
Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current. J. Circuits Syst. Comput. 23(3) (2014) - [j17]Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda:
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 686-690 (2014) - 2012
- [j16]Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. 6(4): 260-270 (2012) - [j15]Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin'ichiro Mutoh, Masayuki Miyama, Yoshio Matsuda:
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2301-2314 (2012) - 2011
- [j14]Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 230-234 (2011) - [c7]Masayuki Miyama, Yoshio Matsuda:
Vehicle detection and tracking with affine motion segmentation in stereo video. ICSIPA 2011: 271-276 - 2010
- [j13]Shunji Nakata, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda:
Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. IEICE Electron. Express 7(9): 640-646 (2010) - [j12]Katsumi Dosaka, Daisuke Ogawa, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda:
A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications. IEICE Trans. Electron. 93-C(5): 685-695 (2010) - [j11]Yoshiki Yunbe, Masayuki Miyama, Yoshio Matsuda:
A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation. IEICE Trans. Inf. Syst. 93-D(12): 3284-3293 (2010) - [j10]Shunji Nakata, Masayuki Miyama, Yoshio Matsuda:
Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system. IET Circuits Devices Syst. 4(4): 301-311 (2010) - [c6]Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda:
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. ISCAS 2010: 2474-2477
2000 – 2009
- 2009
- [c5]Shunji Nakata, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda:
Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage. ISCAS 2009: 393-396 - 2008
- [j9]Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto:
A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. IEICE Trans. Electron. 91-C(4): 457-464 (2008) - [j8]Masayuki Miyama, Yuusuke Inoie, Takafumi Kasuga, Ryouichi Inada, Masashi Nakao, Yoshio Matsuda:
A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(8): 2025-2034 (2008) - 2006
- [j7]Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Hideo Ohira, Masayuki Miyama, Masahiko Yoshimoto:
A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor. Intell. Autom. Soft Comput. 12(3): 283-298 (2006) - [j6]Noriyuki Minegishi, Junichi Miyakoshi, Yuki Kuroda, Tadayoshi Katagiri, Yuki Fukuyama, Ryo Yamamoto, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation. IEICE Trans. Electron. 89-C(3): 230-242 (2006) - [j5]Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto:
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3623-3633 (2006) - 2005
- [j4]Junichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto:
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. IEICE Trans. Electron. 88-C(4): 559-569 (2005) - [j3]Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Masayuki Miyama, Masahiko Yoshimoto:
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3290-3297 (2005) - [j2]Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto:
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3492-3499 (2005) - 2004
- [j1]Masayuki Miyama, Junichi Miyakoshi, Yuki Kuroda, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. IEEE J. Solid State Circuits 39(9): 1562-1570 (2004) - [c4]Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. ASP-DAC 2004: 527-528 - 2003
- [c3]Junichi Miyakoshi, Yuri Kuroda, Masayuki Miyama, Kosuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. CICC 2003: 181-184 - 2002
- [c2]Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto:
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. CICC 2002: 167-170 - 2001
- [c1]Akira Watanabe, Osamu Tooyama, Masayuki Miyama, Masahiko Yoshimoto, Junichi Akita:
An image sensor with fast extraction of objects' positions - rough vision processor. ICIP (2) 2001: 1105-1108
Coauthor Index
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