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ORCIDDaniel G. Saab
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- affiliation: Case Western Reserve University, USA
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Journal Articles
- 2009
[j19]Fatih Kocan, Lun Li, Daniel G. Saab:
Exact Path Delay Fault Coverage Calculation of Partitioned Circuits. IEEE Trans. Computers 58(6): 858-864 (2009)- 2007
- [j18]Fatih Kocan, Daniel G. Saab:
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware. J. Electron. Test. 23(5): 405-420 (2007) - 2002
- [j17]Fatih Kocan, Daniel G. Saab:
Correction to "ATPG for combinational circuits on configurable hardware". IEEE Trans. Very Large Scale Integr. Syst. 10(3): 374-374 (2002) - 2001
- [j16]Fatih Kocan, Daniel G. Saab:
ATPG for combinational circuits on configurable hardware. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 117-129 (2001) - 1999
- [j15]Ben Mathew, Daniel G. Saab:
Combining multiple DFT schemes with test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 685-696 (1999) - 1998
- [j14]Jalal A. Wehbeh, Daniel G. Saab:
Initialization of Sequential Circuits and its Application to ATPG. J. Electron. Test. 13(3): 259-271 (1998) - 1996
- [j13]Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab:
Site Partitioning for Redundant Arrays of Distributed Disks. J. Parallel Distributed Comput. 33(1): 1-11 (1996) - [j12]Daniel G. Saab, Youssef Saab, Jacob A. Abraham:
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1278-1285 (1996) - 1994
- [j11]Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab:
Structural and behavioral synthesis for testability techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 777-785 (1994) - [j10]Ben Mathew, Daniel G. Saab:
Partial Reset: An Alternative DFT Approach. VLSI Design 1(4): 299-311 (1994) - 1993
- [j9]Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab:
Recovery Issues in Databases Using Redundant Disk Arrays. J. Parallel Distributed Comput. 17(1-2): 75-89 (1993) - [j8]Robert B. Mueller-Thuns, Joseph T. Rahmeh, Jacob A. Abraham, Jalal A. Wehbeh, Daniel G. Saab:
Concurrent Hierarchical and Multilevel Simulation of VLSI Circuits. Simul. 60(2): 79-91 (1993) - [j7]Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham:
VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(3): 446-460 (1993) - [j6]Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj:
Switch-level timing simulation of bipolar ECL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4): 516-530 (1993) - [j5]Chung-Hsing Chen, Daniel G. Saab:
A novel behavioral testability measure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1960-1970 (1993) - [j4]Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham:
Benchmarking Parallel Processing Platforms: An Applications Perspective. IEEE Trans. Parallel Distributed Syst. 4(8): 947-954 (1993) - [j3]Daniel G. Saab:
Parallel-concurrent fault simulation. IEEE Trans. Very Large Scale Integr. Syst. 1(3): 356-364 (1993) - 1990
- [j2]Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham:
Hierarchical multi-level fault simulation of large systems. J. Electron. Test. 1(2): 139-149 (1990) - 1987
- [j1]Ibrahim N. Hajj, Daniel G. Saab:
Switch-Level Logic Simulation of Digital Bipolar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(2): 251-258 (1987)
Conference and Workshop Papers
- 2018
- [c59]Ninghan Tian, Daniel G. Saab, Jacob A. Abraham:
ESIFT: Efficient System for Error Injection. IOLTS 2018: 201-206 - 2017
- [c58]Tong Zhang, Daniel G. Saab, Jacob A. Abraham:
Automatic Assertion Generation for Simulation, Formal Verification and Emulation. ISVLSI 2017: 471-476 - 2016
- [c57]Harini Bhamidipati, Daniel G. Saab, Jacob A. Abraham:
Single Trojan injection model generation and detection. LATS 2016: 181 - 2015
- [c56]Gregory Ford, Aswin Krishna, Jacob A. Abraham, Daniel G. Saab:
Formal Verification ATPG Search Engine Emulator (Abstract Only). FPGA 2015: 264 - 2012
- [c55]Sijing Han, Vijay Sirigiri, Daniel G. Saab, Massood Tabib-Azar
:
Ultra-low power NEMS FPGA. ICCAD 2012: 533-538 - 2011
- [c54]Khawla Alzoubi, Daniel G. Saab, Sijing Han, Massood Tabib-Azar:
Complementary Nano-Electro-Mechanical Switch for ultra-low-power applications: Design and modeling. ISQED 2011: 728-735 - 2010
- [c53]Vijay K. Sirigir, Khawla Alzoubi, Daniel G. Saab, Fatih Kocan, Massood Tabib-Azar:
Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGA. FPL 2010: 368-373 - 2009
- [c52]Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar:
Complementary nano-electromechanical switches for ultra-low power embedded processors. ACM Great Lakes Symposium on VLSI 2009: 309-314 - 2007
- [c51]Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab:
Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. ASP-DAC 2007: 86-91 - [c50]Jason Meyer, Fatih Kocan, Daniel G. Saab:
Critical Path Delay Reduction in FPGAs with Unbalanced Lookup Times. ERSA 2007: 182-190 - [c49]Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab:
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. ETS 2007: 173-178 - [c48]Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham:
Reducing verification overhead with RTL slicing. ACM Great Lakes Symposium on VLSI 2007: 399-404 - [c47]Jacob A. Abraham, Daniel G. Saab:
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. VLSI Design 2007: 6 - 2006
- [c46]Jen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham:
HDL Program Slicing to Reduce Bounded Model Checking Search Overhead. ITC 2006: 1-7 - [c45]Qiang Qiang, Daniel G. Saab, Jacob A. Abraham:
Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. VLSI Design 2006: 225-230 - 2005
- [c44]Qiang Qiang, Daniel G. Saab, Jacob A. Abraham:
An Emulation Model for Sequential ATPG-Based Bounded Model Checking. FPL 2005: 469-474 - [c43]Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham:
Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. ICCD 2005: 461-463 - 2003
- [c42]Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula:
Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. VLSI Design 2003: 243-248 - 2002
- [c41]Daniel G. Saab, Fatih Kocan, Jacob A. Abraham:
Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. FPL 2002: 1172-1176 - [c40]Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab:
Verifying Properties Using Sequential ATPG. ITC 2002: 194-202 - 2000
- [c39]Tarachand Pagarani, Fatih Kocan, Daniel G. Saab, Jacob A. Abraham:
Parallel and scalable architecture for solving SATisfiability on reconfigurable FPGA. CICC 2000: 147-150 - [c38]Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab:
Hierarchical Test Generation for Systems On a Chip. VLSI Design 2000: 198- - 1999
- [c37]Miron Abramovici, José T. de Sousa, Daniel G. Saab:
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. DAC 1999: 684-690 - [c36]Fatih Kocan, Daniel G. Saab:
Dynamic Fault Diagnosis on Reconfigurable Hardware. DAC 1999: 691-696 - [c35]Fatih Kocan, Daniel G. Saab:
Concurrent D-algorithm on reconfigurable hardware. ICCAD 1999: 152-156 - 1998
- [c34]Fatih Kocan, Daniel G. Saab:
Dynamic fault diagnosis for sequential circuits on reconfigurable hardware. ICCD 1998: 214-215 - 1997
- [c33]Miron Abramovici, Daniel G. Saab:
Satisfiability on reconfigurable hardware. FPL 1997: 448-456 - 1996
- [c32]Jalal A. Wehbeh, Daniel G. Saab:
Initialization of sequential circuits and its application to ATPG. VTS 1996: 246-253 - 1995
- [c31]Ben Mathew, Daniel G. Saab:
DFT & ATPG: Together Again. ITC 1995: 262-271 - 1994
- [c30]Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel:
Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. EDAC-ETC-EUROASIC 1994: 40-45 - [c29]Jalal A. Wehbeh, Daniel G. Saab:
Efficient simulation of switch-level circuits in a hierarchical simulation environment. Great Lakes Symposium on VLSI 1994: 231-235 - [c28]Daniel G. Saab, Youssef Saab, Jacob A. Abraham:
Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. ICCAD 1994: 40-43 - [c27]Jalal A. Wehbeh, Daniel G. Saab:
On the Initialization of Sequential Circuits. ITC 1994: 233-239 - 1993
- [c26]Gwan S. Choi, Ravishankar K. Iyer, Daniel G. Saab:
Fault behavior dictionary for simulation of device-level transients. ICCAD 1993: 6-9 - [c25]Ben Mathew, Daniel G. Saab:
Augmented partial reset. ICCAD 1993: 716-719 - [c24]Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab:
Assigning Sites fto Redundant Clusters in a Distributed Storage System. ICPP (1) 1993: 64-71 - [c23]Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab:
Performance of Redundant Disk Array Organizations in Transaction Processing Environments. ICPP (1) 1993: 138-145 - [c22]Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab:
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. ITC 1993: 606-615 - [c21]Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab:
On Selecting Flip-Flops for Partial Reset. ITC 1993: 1008-1012 - 1992
- [c20]Daniel G. Saab, Youssef Saab, Jacob A. Abraham:
CRIS: a test cultivation program for sequential VLSI circuits. ICCAD 1992: 216-219 - [c19]Chung-Hsing Chen, Daniel G. Saab:
Behavioral synthesis for testability. ICCAD 1992: 612-615 - [c18]Jalal A. Wehbeh, Daniel G. Saab:
Hierarchical Simulation of MOS Circuits Using Extracted Functional Models. ICCD 1992: 512-515 - [c17]Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab:
Database Recovery Using Redundant Disk Arrays. ICDE 1992: 176-183 - [c16]Antoine N. Mourad, W. Kent Fuchs, Daniel G. Saab:
Site Partitioning for Distributed Redundant Disk Arrays. RIDE-TQP 1992: 214 - [c15]Ben Mathew, Daniel G. Saab:
Robust switch-level test generation. VTS 1992: 107-112 - 1991
- [c14]Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham:
Parallel switch-level simulation for VLSI. EURO-DAC 1991: 324-328 - [c13]David T. Blaauw, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham:
Functional abstraction of logic gates for switch-level simulation. EURO-DAC 1991: 329-333 - [c12]Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab:
BETA: Behavioral Testability Analysis. ICCAD 1991: 202-205 - [c11]Chung-Hsing Chen, Chienwen Wu, Daniel G. Saab:
Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability. ICCD 1991: 463-466 - [c10]Stanford S. Guillory, Daniel G. Saab, Andrew T. Yang:
Fault modeling and testing of self-timed circuits. VTS 1991: 62-66 - 1990
- [c9]David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham:
Derivation of signal flow for switch-level simulation. EURO-DAC 1990: 301-305 - [c8]David T. Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham:
SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69 - [c7]Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Joseph T. Rahmeh, Jacob A. Abraham:
Fault grading of large digital systems. ICCD 1990: 290-293 - [c6]Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham:
Design of a scalable parallel switch-level simulator for VLSI. SC 1990: 615-624 - 1989
- [c5]David T. Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh:
Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184 - [c4]Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham:
Portable parallel logic and fault simulation. ICCAD 1989: 506-509 - [c3]Daniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh:
Parallel-concurrent fault simulation. ICCD 1989: 298-301 - 1988
- [c2]Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj:
Delay Modeling and Time of Bipolar Digital Circuits. DAC 1988: 288-293 - [c1]Daniel G. Saab, Robert B. Mueller-Thuns, David T. Blaauw, Jacob A. Abraham, Joseph T. Rahmeh:
CHAMP: concurrent hierarchical and multilevel program for simulation of VLSI circuits. ICCAD 1988: 246-249
Coauthor Index
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