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ORCIDAntonio Lloris-Ruíz
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Journal Articles
- 2017
[j9]Encarnación Castillo
, Antonio Lloris-Ruíz, Diego Pedro Morales, Luis Parrilla, Antonio García, Guillermo Botella:
A new area-efficient BCD-digit multiplier. Digit. Signal Process. 62: 1-10 (2017)- 2016
- [j8]Encarnación Castillo, Antonio Lloris-Ruíz, Antonio García, Luis Parrilla, Diego Pedro Morales:
Comments on "Fast architecture for decimal digit multiplication". Microprocess. Microsystems 47: 441-444 (2016) - 2007
- [j7]Encarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz:
IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 578-591 (2007) - 2003
- [j6]Javier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz:
Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic. J. VLSI Signal Process. 33(1-2): 171-190 (2003) - [j5]Javier Ramírez, Uwe Meyer-Bäse, Fred J. Taylor, Antonio García, Antonio Lloris-Ruíz:
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies. J. VLSI Signal Process. 34(3): 227-237 (2003) - 1999
- [j4]Antonio García, Antonio Lloris-Ruíz:
A Look-Up Scheme for Scaling in the RNS. IEEE Trans. Computers 48(7): 748-751 (1999) - 1993
- [j3]Pablo P. Trabado, Antonio Lloris-Ruíz, Julio Ortega Lopera:
Solution of Switching Equations Based on a Tabular Algebra. IEEE Trans. Computers 42(5): 591-596 (1993) - [j2]Julio Ortega Lopera, Alberto Prieto, Antonio Lloris-Ruíz, Francisco J. Pelayo:
Generalized Hopfield Neural Network for Concurrent Testing. IEEE Trans. Computers 42(8): 898-912 (1993) - [j1]Julio Ortega Lopera, Antonio Lloris-Ruíz, Alberto Prieto, Francisco J. Pelayo:
Test-Pattern Generation Based on Reed-Muller Coefficients. IEEE Trans. Computers 42(8): 968-980 (1993)
Conference and Workshop Papers
- 2007
- [c19]Encarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz:
Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. FPL 2007: 183-188 - 2006
- [c18]Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris-Ruíz, Uwe Meyer-Bäse:
IPP Watermarking Technique for IP Core Protection on FPL Devices. FPL 2006: 1-6 - 2005
- [c17]Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz:
Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. FPL 2005: 531-534 - [c16]Daniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz:
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. PATMOS 2005: 657-665 - 2004
- [c15]Luis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz:
Intellectual Property Protection for RNS Circuits on FPGAs. FPL 2004: 1139-1141 - 2003
- [c14]Javier Ramírez, Uwe Meyer-Bäse, Antonio García, Antonio Lloris-Ruíz:
Design and Implementation of RNS-Based Adaptive Filters. FPL 2003: 1135-1138 - 2002
- [c13]Daniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris-Ruíz:
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. PATMOS 2002: 188-197 - 2001
- [c12]Javier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Pedro G. Fernández, Antonio Lloris-Ruíz:
Design of RNS-based distributed arithmetic DWT filterbanks. ICASSP 2001: 1193-1196 - [c11]Pedro G. Fernández, Javier Ramírez, Antonio García, Luis Parrilla, Antonio Lloris-Ruíz:
Implementation of the one dimensional discrete cosine transform using the residue number system. ICECS 2001: 433-436 - 2000
- [c10]Javier Ramírez, Antonio García, Pedro G. Fernández, Antonio Lloris-Ruíz:
An efficient RNS architecture for the computation of discrete wavelet transforms on programmable devices. EUSIPCO 2000: 1-4 - [c9]Javier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz:
Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. FPL 2000: 342-351 - [c8]Javier Ramírez Perez de Inestrosa, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz:
A new architecture to compute the discrete cosine transform using the quadratic residue number system. ISCAS 2000: 321-324 - 1999
- [c7]Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, Fred J. Taylor:
RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic. ISCAS (1) 1999: 486-489 - [c6]Luis Parrilla, Julio Ortega, Antonio Lloris-Ruíz:
Using PVM for Distributed Logic Minimization in a Network of Computers. PVM/MPI 1999: 541-548 - 1998
- [c5]Antonio García, Antonio Lloris-Ruíz:
Pipelined RNS multipliers: an application to scaling. ICECS 1998: 55-58 - [c4]Luis Parrilla, Julio Ortega, Antonio Lloris-Ruíz:
Testability of AND-EXOR logic vs. AND-OR logic. ICECS 1998: 213-216 - 1997
- [c3]Julio Ortega, Luis Parrilla, Alberto Prieto, Antonio Lloris-Ruíz, Carlos García Puntonet:
Modified Boltzmann Machine for an Efficient Distributed Implementation. IWANN 1997: 1221-1232 - 1993
- [c2]Antonio Lloris-Ruíz, Juan Francisco Gómez-Lopera, Ramón Román-Roldán:
Entropic Minimization of Multiple-Valued Functions. ISMVL 1993: 24-28 - 1991
- [c1]Julio Ortega, Alberto Prieto, Francisco J. Pelayo, Antonio Lloris-Ruíz, P. Martin-Smith:
Optimization Problems on Concurrent Testing Solved by Neural Networks. IWANN 1991: 385-400
Coauthor Index
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