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Qilin Zheng
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2020 – today
- 2024
- [c12]Yitu Wang, Shiyu Li, Qilin Zheng, Linghao Song, Zongwang Li, Andrew Chang, Hai Li, Yiran Chen:
NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing. ISCA 2024: 368-381 - [c11]Qilin Zheng, Shiyu Li, Yitu Wang, Ziru Li, Yiran Chen, Hai (Helen) Li:
Hybrid Digital/Analog Memristor-based Computing Architecture for Sparse Deep Learning Acceleration. ISCAS 2024: 1-5 - [c10]Zhixu Du, Shiyu Li, Yuhao Wu, Xiangyu Jiang, Jingwei Sun, Qilin Zheng, Yongkai Wu, Ang Li, Hai Li, Yiran Chen:
SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models. MLSys 2024 - [i5]Jonathan Ku, Junyao Zhang, Haoxuan Shan, Saichand Samudrala, Jiawen Wu, Qilin Zheng, Ziru Li, J. V. Rajendran, Yiran Chen:
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM. CoRR abs/2402.14152 (2024) - 2023
- [j6]Pouya Houshmand
, Giuseppe Maria Sarda
, Vikram Jain
, Kodai Ueyoshi
, Ioannis A. Papistas
, Man Shi
, Qilin Zheng, Debjyoti Bhattacharjee
, Arindam Mallik, Peter Debacker
, Diederik Verkest, Marian Verhelst
:
DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. IEEE J. Solid State Circuits 58(1): 203-215 (2023) - [j5]Ziru Li
, Qilin Zheng, Yiran Chen
, Hai Helen Li
:
SpikeSen: Low-Latency In-Sensor-Intelligence Design With Neuromorphic Spiking Neurons. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 1876-1880 (2023) - [j4]Yitu Wang
, Shiyu Li
, Qilin Zheng
, Andrew Chang
, Hai Li
, Yiran Chen
:
EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference. ACM Trans. Embed. Comput. Syst. 22(5s): 100:1-100:22 (2023) - [c9]Yimao Cai, Yi Gao, Zongwei Wang, Lin Bao, Ling Liang, Qilin Zheng, Cuimei Wang, Ru Huang:
Device-Architecture Co-optimization for RRAM-based In-memory Computing. ASICON 2023: 1-4 - [c8]Xiaoxuan Yang
, Shiyu Li, Qilin Zheng, Yiran Chen:
Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design. ASP-DAC 2023: 618-623 - [c7]Qilin Zheng, Shiyu Li, Yitu Wang, Ziru Li, Yiran Chen, Hai Helen Li:
Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture. DAC 2023: 1-6 - [i4]Xueying Wu, Edward Hanson, Nansu Wang, Qilin Zheng, Xiaoxuan Yang, Huanrui Yang, Shiyu Li, Feng Cheng, Partha Pratim Pande, Janardhan Rao Doppa, Krishnendu Chakrabarty, Hai Li:
Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators. CoRR abs/2310.12182 (2023) - [i3]Zhixu Du, Shiyu Li, Yuhao Wu, Xiangyu Jiang, Jingwei Sun, Qilin Zheng, Yongkai Wu, Ang Li, Hai (Helen) Li, Yiran Chen:
SiDA: Sparsity-Inspired Data-Aware Serving for Efficient and Scalable Large Mixture-of-Experts Models. CoRR abs/2310.18859 (2023) - [i2]Yitu Wang, Shiyu Li, Qilin Zheng, Linghao Song, Zongwang Li, Andrew Chang, Hai (Helen) Li, Yiran Chen:
In-Storage Acceleration of Graph-Traversal-Based Approximate Nearest Neighbor Search. CoRR abs/2312.03141 (2023) - 2022
- [j3]Qilin Zheng, Pingyu Zhu, Shichuan Xue, Yang Wang, Chao Wu, Xinyao Yu, Miaomiao Yu, Yingwen Liu, Mingtang Deng
, Junjie Wu, Ping Xu:
Quantum algorithm and experimental demonstration for the subset sum problem. Sci. China Inf. Sci. 65(8): 1-14 (2022) - [j2]Qilin Zheng
, Xingchen Li
, Yijin Guan, Zongwei Wang
, Yimao Cai
, Yiran Chen
, Guangyu Sun, Ru Huang:
PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5464-5475 (2022) - [j1]Brady Taylor
, Qilin Zheng, Ziru Li
, Shiyu Li
, Yiran Chen
:
Processing-in-Memory Technology for Machine Learning: From Basic to ASIC. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2598-2603 (2022) - [c6]Ziru Li, Qilin Zheng, Bonan Yan, Ru Huang, Bing Li, Yiran Chen:
ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses. DAC 2022: 1099-1104 - [c5]Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda
, Vikram Jain
, Man Shi, Qilin Zheng, Juan Sebastian Piedrahita Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee
, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst
:
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. ISSCC 2022: 1-3 - [i1]Yizhi Wang, Yingwen Liu, Junwei Zhan, Shichuan Xue, Yuzhen Zheng, Ru Zeng, Zhihao Wu, Zihao Wang, Qilin Zheng, Dongyang Wang, Weixu Shi, Xiang Fu, Ping Xu, Yang Wang, Yong Liu, Jiangfang Ding, Guangyao Huang, Chunlin Yu, Anqi Huang, Xiaogang Qiang, Mingtang Deng, Weixia Xu, Kai Lu, Xuejun Yang, Junjie Wu:
Large-scale full-programmable quantum walk and its applications. CoRR abs/2208.13186 (2022) - 2020
- [c4]Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li:
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. DAC 2020: 1-6 - [c3]Qilin Zheng, Xingchen Li
, Zongwei Wang, Guangyu Sun, Yimao Cai, Ru Huang, Yiran Chen, Hai Li:
MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory Block. ICCAD 2020: 104:1-104:9
2010 – 2019
- 2019
- [c2]Qilin Zheng, Jian Kang, Zongwei Wang
, Yimao Cai, Ru Huang, Bing Li, Yiran Chen, Hai Helen Li:
Enhance the Robustness to Time Dependent Variability of ReRAM-Based Neuromorphic Computing Systems with Regularization and 2R Synapse. ISCAS 2019: 1-5 - 2018
- [c1]Qilin Zheng, Zongwei Wang
, Jian Kang, Zhizhen Yu, Yimao Cai, Jintong Xu:
Hiearchical Crossbar Design for ReRAM based Write Variation Inhibition on-chip learning. NVMTS 2018: 1-3
Coauthor Index
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last updated on 2024-08-18 00:34 CEST by the dblp team
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