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ORCIDAlexander Saldanha
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2000 – 2009
- 2007
[j7]Wilsin Gosti, Tiziano Villa, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
:
FSM Encoding for BDD Representations. Int. J. Appl. Math. Comput. Sci. 17(1): 113-124 (2007)- 2000
- [c23]Eugene Goldberg, Alexander Saldanha:
Timing Analysis with Implicitly Specified False Paths. VLSI Design 2000: 518-522
1990 – 1999
- 1999
- [c22]Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli:
A methodology for correct-by-construction latency insensitive design. ICCAD 1999: 309-315 - [c21]Alexander Saldanha:
Functional timing optimization. ICCAD 1999: 539-543 - 1998
- [j6]Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin:
Partial-scan delay fault testing of asynchronous circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1184-1199 (1998) - [c20]Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha:
An Exact Input Encoding Algorithm for BDDs Representing FSMs. Great Lakes Symposium on VLSI 1998: 294-300 - 1997
- [j5]Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Symbolic two-level minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 692-708 (1997) - [c19]Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton:
Approximate timing analysis of combinational circuits under the XBD0 model. ICCAD 1997: 176-181 - [c18]Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli:
Trace driven logic synthesis - application to power minimization. ICCAD 1997: 581-588 - [c17]Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin:
Partial scan delay fault testing of asynchronous circuits. ICCAD 1997: 728-735 - 1996
- [c16]Alberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha:
Verification of Electronic Systems. DAC 1996: 106-111 - [c15]Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Compact and complete test set generation for multiple stuck-faults. ICCAD 1996: 212-219 - 1995
- [j4]William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Delay fault coverage, test set size, and performance trade-offs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1): 32-44 (1995) - [c14]Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha:
Supervisory Control of Finite State Machines. CAV 1995: 279-292 - [c13]Luciano Lavagno, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli:
Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool. DAC 1995: 254-260 - [c12]Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia:
Fast discrete function evaluation using decision diagrams. ICCAD 1995: 402-407 - [c11]Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Functional clock schedule optimization. VLSI Design 1995: 93-98 - 1994
- [j3]Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Satisfaction of input and output encoding constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 589-602 (1994) - [j2]Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Circuit structure relations to redundancy and delay. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 875-883 (1994) - [c10]Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance Optimization Using Exact Sensitization. DAC 1994: 425-429 - 1993
- [c9]William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Delay Fault Coverage and Performance Tradeoffs. DAC 1993: 446-452 - 1992
- [c8]Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. DAC 1992: 173-176 - [c7]Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. DAC 1992: 245-248 - 1991
- [j1]Kurt Keutzer, Sharad Malik, Alexander Saldanha:
Is redundancy necessary to reduce delay? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 427-435 (1991) - [c6]Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A Framework for Satisfying Input and Output Encoding Constraints. DAC 1991: 170-175 - [c5]Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. ICCAD 1991: 180-183 - 1990
- [c4]Kurt Keutzer, Sharad Malik, Alexander Saldanha:
Is Redundancy Necessary to Reduce Delay. DAC 1990: 228-234 - [c3]Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng:
Timing Optimization with Testability Considerations. ICCAD 1990: 460-463
1980 – 1989
- 1989
- [c2]Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Multi-level Logic Simplification Using Don't Cares and Filters. DAC 1989: 277-282 - 1988
- [c1]Alexander Saldanha, Randy H. Katz:
PLA optimization using output encoding. ICCAD 1988: 478-481
Coauthor Index
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