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ORCIDJaeseung Choi 0001
Person information
- affiliation: Samsung Electronics, Hwaseong, Korea
Other persons with the same name
- Jaeseung Choi 0002
![[0000-0002-5493-9174]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-5493-9174")
— Sogang University, Korea (and 1 more)
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2020 – today
- 2023
[c8]Gyuseong Kang, Hyunjin Shin, Hyuntaek Jung, Sunkyu Lee, Jaeseung Choi, Sangyeop Baeck, Hyunsung Jung, Daeshik Kim, Sohee Hwang, Shinhee Han, Yongsung Ji, Sei Seung Yoon:
A 14nm 128Mb Embedded MRAM Macro achieved the Best Figure-Of-Merit with 80MHz Read operation and 18.1Mb/mm² implementation at 0.64V. VLSI Technology and Circuits 2023: 1-2- 2022
- [c7]Hyunjin Shin, Sangkyung Won, Dohui Kim, Byunghun Choi, Gyusung Kim, Myeonghee Oh, Jaeseung Choi, Jongwook Kye:
A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm2 at 0.85V. VLSI Technology and Circuits 2022: 132-133 - 2021
- [c6]Sangyeop Baeck, Inhak Lee, Hoyoung Tang, Dongwook Seo, Jaeseung Choi, Taejoong Song, Jongwook Kye:
5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application. VLSI Circuits 2021: 1-2 - [c5]Hyunjin Shin, Myeonghee Oh, Jaeseung Choi, Taejoong Song, Jongwook Kye:
A 28nm Embedded Flash Memory with 100MHz Read Operation and 7.42Mb/mm2 at 0.85V featuring for Automotive Application. VLSI Circuits 2021: 1-2
2010 – 2019
- 2019
- [c4]Inhak Lee, Hanwool Jeong, Sangyeop Baeck, Siddharth Gupta, Changnam Park, Dongwook Seo, Jaeseung Choi, Jaeyoung Kim, Hoon Kim, Jungmyung Kang, Sunyung Jang, Daeyoung Moon, Sangshin Han, Taehyung Kim, Jaehyun Lim, Younghwan Park, Hyejin Hwang, Jeonseung Kang, Taejoong Song:
A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology. ISSCC 2019: 392-394 - 2018
- [c3]Taejoong Song, Jonghoon Jung, Woojin Rim, Hoonki Kim, Yongho Kim, Changnam Park, Jeongho Do, Sunghyun Park, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, Jaeseung Choi, Jong Shik Yoon:
A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. ISSCC 2018: 198-200 - 2017
- [j1]Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Giyong Yang, Hoonki Kim, Sanghoon Baek, Jonghoon Jung, Bongjae Kwon, Sungwee Cho, Hyuntaek Jung, Yongjae Choo, Jaeseung Choi:
A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization. IEEE J. Solid State Circuits 52(1): 240-249 (2017) - [c2]Taejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi:
12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. ISSCC 2017: 208-209 - 2016
- [c1]Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Jonghoon Jung, Giyong Yang, Sanghoon Baek, Jaeseung Choi, Bongjae Kwon, Yunwoo Lee, Sungbong Kim, Gyu-Hong Kim, Hyo-Sig Won, Ja-Hum Ku, Sunhom Steve Paak, E. S. Jung, Steve Sungho Park, Kinam Kim:
17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. ISSCC 2016: 306-307
Coauthor Index
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