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ORCIDKenichi Miyaguchi
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2020 – today
- 2022
[c8]Rongmei Chen, Giuliano Sisto
, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne:
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node. VLSI Technology and Circuits 2022: 429-430- 2021
- [c7]Kenichi Miyaguchi, Yoojin Ban, Nicolas Pantano, Xiao Sun, Philippe Absil, Lieve Bogaerts, Peter Verheyen, Dimitrios Velenis, Marianna Pantouvaki, Joris Van Campenhout:
110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules. ECOC 2021: 1-4 - 2020
- [c6]Alessio Spessot, Bertrand Parvais, Amita Rawat, Kenichi Miyaguchi, Pieter Weckx, Doyoung Jang, Julien Ryckaert:
Device Scaling roadmap and its implications for Logic and Analog platform. BCICTS 2020: 1-8
2010 – 2019
- 2017
- [c5]Fabian M. Bufler, Kenichi Miyaguchi, Thomas Chiarella, N. Horiguchi, Anda Mocuta:
On the ballistic ratio in 14nm-Node FinFETs. ESSDERC 2017: 176-179 - 2015
- [j1]Halil Kükner, Pieter Weckx, Sébastien Morrison, Jacopo Franco, Maria Toledano-Luque, Moonju Cho, Praveen Raghavan, Ben Kaczer, Doyoung Jang, Kenichi Miyaguchi, Marie Garcia Bardon, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken:
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. Microprocess. Microsystems 39(8): 1039-1051 (2015) - [c4]Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean:
Modeling FinFET metal gate stack resistance for 14nm node and beyond. ICICDT 2015: 1-4 - [c3]Kazuyuki Tomida, Keizo Hiraga, Morin Dehan, Geert Hellings, Doyoung Jang, Kenichi Miyaguchi, Thomas Chiarella, Minsoo Kim, Anda Mocuta, Naoto Horiguchi, Abdelkarim Mercha, Diederik Verkest, Aaron Thean:
Impact of fin shape variability on device performance towards 10nm node. ICICDT 2015: 1-4 - 2014
- [c2]Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, Philippe Leray, Tsung-Te Liu, Kenichi Miyaguchi, Bertrand Parvais, Pieter Schuddinck, Philippe Weemaes, Abdelkarim Mercha, Jürgen Bömmels, Naoto Horiguchi, Greg McIntyre, Aaron Thean, Zsolt Tökei, Shaunee Cheng, Diederik Verkest, An Steegen:
Design Technology co-optimization for N10. CICC 2014: 1-8 - 2013
- [c1]Doyoung Jang, Marie Garcia Bardon, Dmitry Yakimets, Kenichi Miyaguchi, An De Keersgieter, Thomas Chiarella, Romain Ritzenthaler, Morin Dehan, Abdelkarim Mercha:
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process. ESSDERC 2013: 159-162
Coauthor Index
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