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ORCIDJia Zhan
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2020 – today
- 2024
[j6]Jia Zhan
, Francis C. M. Lau:
Design of Joint Source-Channel Coding Scheme Based on Spatially-Coupled DP-LDPC Codes. IEEE Commun. Lett. 28(4): 749-753 (2024)- 2023
- [j5]Jia Zhan, Francis C. M. Lau:
Joint Design of Source-Channel Codes With Linear Source Encoding Complexity and Good Channel Thresholds Based on Double-Protograph LDPC Codes. IEEE Commun. Lett. 27(11): 2909-2913 (2023) - [i2]Jia Zhan, Francis C. M. Lau:
Joint Design of Source-Channel Codes with Linear Source Encoding Complexity and Good Channel Thresholds Based on Double-Protograph LDPC Codes. CoRR abs/2309.14653 (2023) - 2022
- [c13]Longyu Ma, Chiu-Wing Sham, Jia Zhan, Francis C. M. Lau:
Implementation for JSCC Scheme Based on QC-LDPC Codes. GCCE 2022: 292-295 - [i1]Jia Zhan, Francis C. M. Lau:
Design of Joint Source-Channel Codes Based on a Single Protograph. CoRR abs/2205.08121 (2022) - 2021
- [c12]Francis C. M. Lau, Jia Zhan:
Joint Source-Channel Codes Based on a Single Protograph. ISTC 2021: 1-5 - 2020
- [j4]Hongli Cao, Liang Fang, Lin Chen, Jia Zhan, Xuehong Diao, Yingchun Liu, Chen Lu, Zhengwang Zhang, Yue Chen:
The independent indicators for differentiating renal cell carcinoma from renal angiomyolipoma by contrast-enhanced ultrasound. BMC Medical Imaging 20(1): 32 (2020)
2010 – 2019
- 2018
- [c11]Chang Liu, Wen-jun Xie, Peng Zhang, Jia Zhan, Zonghao Xiao:
Considerations on Multimodal Human-Computer Interaction. CCIS 2018: 331-335 - 2017
- [j3]Jia Zhan, Lin Wang, Marcos Katz, Guanrong Chen:
A Differential Chaotic Bit-Interleaved Coded Modulation System Over Multipath Rayleigh Channels. IEEE Trans. Commun. 65(12): 5257-5265 (2017) - 2016
- [j2]Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie:
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3041-3054 (2016) - [c10]Itir Akgun, Jia Zhan, Yuangang Wang, Yuan Xie:
Scalable memory fabric for silicon interposer-based multi-core systems. ICCD 2016: 33-40 - [c9]Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita R. Das, Yuan Xie:
OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures. MICRO 2016: 28:1-28:13 - [c8]Jia Zhan, Itir Akgun, Jishen Zhao, Al Davis, Paolo Faraboschi, Yuangang Wang, Yuan Xie:
A unified memory network architecture for in-memory computing in commodity servers. MICRO 2016: 29:1-29:14 - 2015
- [c7]Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie:
DimNoC: a dim silicon approach towards power-efficient on-chip network. DAC 2015: 10:1-10:6 - [c6]Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin:
Core vs. uncore: the heart of darkness. DAC 2015: 121:1-121:6 - [c5]Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan:
Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. ISQED 2015: 565-570 - 2014
- [j1]Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie:
Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1632-1643 (2014) - [c4]Qiaosha Zou, Jia Zhan, Fen Ge, Matt Poremba, Yuan Xie:
Designing vertical bandwidth reconfigurable 3D NoCs for many core systems. 3DIC 2014: 1-7 - [c3]Jia Zhan, Matthew Poremba, Yi Xu, Yuan Xie:
NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores. ASP-DAC 2014: 586-591 - [c2]Jia Zhan, Yuan Xie, Guangyu Sun:
NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era. DAC 2014: 160:1-160:6 - 2013
- [c1]Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie:
Designing energy-efficient NoC for real-time embedded systems through slack optimization. DAC 2013: 37:1-37:6
Coauthor Index
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