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ORCIDTun Li 0002
Person information
- affiliation: National University of Defense Technology, College of Computer Science and Technology, Changsha, Hunan, China
Other persons with the same name
- Tun Li — disambiguation page
- Tun Li 0001
![[0000-0002-7190-0167]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-7190-0167")
— Chongqing University of Posts and Telecommunications, Chongqing, China
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2020 – today
- 2025
[j7]Yue Cheng, Tun Li, Hongji Zou, Wanxia Qu:
PyABV: a framework for enhancing PyRTL with assertion-based verification. Frontiers Comput. Sci. 19(7): 197204 (2025)- [j6]Yongtao Luo, Jie Liu, Chunye Gong, Tun Li:
An efficient heterogeneous parallel password recovery system on MT-3000. J. Supercomput. 81(1): 38 (2025) - [c29]Jixiao Deng, Qinglin Wang, Lin Chen, Tun Li, Bo Yang, Xinhai Chen, Jie Liu:
IA-Chol: Input-Aware Cholesky Decomposition on CPU and GPU. ICS 2025: 135-148 - 2024
- [j5]Deheng Yang, Jiayu He, Xiaoguang Mao, Tun Li, Yan Lei, Xin Yi, Jiang Wu:
Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1594-1607 (2024) - 2023
- [c28]Yan Pi, Hongji Zou, Tun Li, Wanxia Qu, Hai Wan:
ESFO: Equality Saturation for FIRRTL Optimization. ACM Great Lakes Symposium on VLSI 2023: 581-586 - [c27]Tun Li, Mingchuan Shi, Hongji Zou, Wanxia Qu:
Towards Accelerating Assertion Coverage Using Surrogate Logic Models. ISCAS 2023: 1-5 - 2022
- [j4]Dan Luo, Tun Li, Liqian Chen, Hongji Zou, Mingchuan Shi:
Grammar-based fuzz testing for microprocessor RTL design. Integr. 86: 64-73 (2022) - [c26]Hongji Zou, Mingchuan Shi, Tun Li, WanXia Qu:
Towards Implementing RTL Microprocessor Agile Design Using Feature Oriented Programming. DATE 2022: 472-477 - 2021
- [c25]Keke Hu, Wanwei Liu, Tun Li:
Rectified Multi-class AdaBoost for Noisy Dataset Based on Weight Adjustment Standard. ASSE 2021: 84-88 - [c24]Tun Li, Wanwei Liu, Liqian Chen, Xiaoguang Mao:
On Enhancing Application-Ability Training in Discrete Mathematics. FIE 2021: 1-5 - [c23]Tun Li, Hongji Zou, Dan Luo, WanXia Qu:
Symbolic Simulation Enhanced Coverage-Directed Fuzz Testing of RTL Design. ISCAS 2021: 1-5 - 2020
- [j3]Tun Li, Wanwei Liu, Xinrui Guo, Ji Wang:
Software testing without the oracle correctness assumption. Frontiers Comput. Sci. 14(3): 143203 (2020) - [c22]Wanwei Liu, Liangze Yin, Tun Li:
Compiling FLres on Finite Words. SETTA 2020: 108-123
2010 – 2019
- 2015
- [c21]Tun Li, Jian Hu, Yang Guo, Sikun Li, QingPing Tan:
Equivalence checking of scheduling in high-level synthesis. ISQED 2015: 257-262 - 2013
- [j2]Rui Wang, Wanwei Liu, Tun Li, Xiaoguang Mao, Ji Wang:
Bounded Model Checking of ETL Cooperating with Finite and Looping Automata Connectives. J. Appl. Math. 2013: 462532:1-462532:12 (2013) - [c20]Tun Li, Dan Zhu, Sikun Li, Yang Guo:
Application specified soft error failure rate analysis using sequential equivalence checking techniques. ASP-DAC 2013: 608-613 - [c19]Tun Li, Yang Guo, Wanwei Liu, Mingsheng Tang:
Translation validation of scheduling in high level synthesis. ACM Great Lakes Symposium on VLSI 2013: 101-106 - [c18]Tun Li, Yang Guo, Wanwei Liu, Chiyuan Ma:
Efficient translation validation of high-level synthesis. ISQED 2013: 516-523 - [c17]Tun Li, Wanwei Liu, Xiaoguang Mao, Huiping Zhou:
Introduction to programming: science or art? ITiCSE 2013: 324
2000 – 2009
- 2008
- [c16]WanXia Qu, Tun Li, Yang Guo, Xiaodong Yang:
Explicit Model Checking Based on Integer Pointer and Fibonacci Hash. ICYCS 2008: 844-849 - [c15]Dan Zhu, Tun Li, Yang Guo, Sikun Li:
2D Decomposition Sequential Equivalence Checking of System Level and RTL Descriptions. ISQED 2008: 637-642 - 2007
- [c14]Yang Guo, WanXia Qu, Tun Li, Sikun Li:
Coverage Driven Test Generation Framework for RTL Functional Verification. CAD/Graphics 2007: 321-326 - [c13]Tun Li, Sikun Li, Jinshan Yu, Yang Guo:
A Novel Collaborative Verification Environment for SoC Co-Verification. CSCWD 2007: 145-150 - [c12]Tun Li, Yang Guo, Sikun Li, Wei Dong, Rangyu Deng:
Experiences Teaching Functional Verification Techniques with Practical Designs. MSE 2007: 93-94 - 2006
- [c11]Jinshan Yu, Tun Li, Yang Guo, QingPing Tan:
Scheduling of Transactions Based on Extended Scheduling Timed Petri Nets for SoC System-Level Test-Case Generation. EUC 2006: 732-741 - 2005
- [c10]Tun Li, Dan Zhu, Lei Liang, Yang Guo, Sikun Li:
Automatic functional test program generation for microprocessor verification. ASP-DAC 2005: 1039-1042 - [c9]Tun Li, Yang Guo, Sikun Li, GongJie Liu:
Predicate Abstraction of RTL Verilog Descriptions Using Constraint Logic Programming. ATVA 2005: 174-186 - [c8]Tun Li, Yang Guo, GongJie Liu, Sikun Li:
Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming. DSD 2005: 17-25 - [c7]Tun Li, Dan Zhu, Yang Guo, GongJie Liu, Sikun Li:
MA2TG: A Functional Test Program Generator for Microprocessor Verification. DSD 2005: 176-183 - [c6]Tun Li, Yang Guo, Sikun Li, Dan Zhu:
Applying Constraint Logic Programming to Predicate Abstraction of RTL Verilog Descriptions. MICAI 2005: 175-184 - 2004
- [j1]Tun Li, Yang Guo, Sikun Li:
Automatic Circuit Extractor for HDL Description Using Program Slicing. J. Comput. Sci. Technol. 19(5): 718-728 (2004) - [c5]Tun Li, Yang Guo, Sikun Li, Fujiang Ao, Gongjie Li:
Parallel verilog simulation: architecture and circuit partition. ASP-DAC 2004: 644-646 - [c4]Tun Li, Yang Guo, Sikun Li:
CLP Based Static Property Checking. ATVA 2004: 495-498 - [c3]Tun Li, Yang Guo, Sikun Li:
Assertion-based automated functional vectors generation using constraint logic programming. ACM Great Lakes Symposium on VLSI 2004: 288-291 - [c2]Tun Li, Yang Guo, Sikun Li:
Design and Implementation of a Parallel Verilog Simulator: PVSim. VLSI Design 2004: 329-334 - 2003
- [c1]Tun Li, Yang Guo, Sikun Li:
An Automatic Circuit Extractor for RTL Verification. Asian Test Symposium 2003: 154-160
Coauthor Index
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